Abov MC97F60128 - Page 162

162
MC97F60128
ABOV Semiconductor Co., Ltd.
TnCR (Timer n Control Register) : D2H/DAH/DDH, Where n = 0, 1 and 2
7
6
5
4
3
2
1
0
TnEN
–
TnMS1
TnMS0
TnCK2
TnCK1
TnCK0
TnCC
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
TnEN
Control Timer n
0
Timer n disable
1
Timer n enable
TnMS[1:0]
Control Timer n Operation Mode
TnMS1
TnMS0
Description
0
0
Timer/counter mode (TnO: toggle at match)
0
1
PWM mode (The overflow interrupt can occur)
1
x
Capture mode (The match interrupt can occur)
TnCK[2:0]
Select Timer n clock source. fx is a system clock frequency
TnCK2
TnCK1
TnCK0
Description
0
0
0
fx/2
0
0
1
fx/4
0
1
0
fx/8
0
1
1
fx/32
1
0
0
fx/128
1
0
1
fx/512
1
1
0
fx/2048
1
1
1
External Clock (ECn)
TnCC
Clear timer n Counter
0
No effect
1
Clear the Timer n counter (When write, automatically cleared “0” after being
cleared counter)