Abov MC97F60128 User Manual

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MC97F60128
ABOV Semiconductor Co., Ltd.
UARTnCR2 (UARTn Control Register 2) : 4061H/4069H/4071H (XSFR), Where n = 2, 3 and 4
7
6
5
4
3
2
1
0
UDRIEn
TXCIEn
RXCIEn
WAKEIEn
TXEn
RXEn
UARTnEN
U2Xn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
UDRIEn
Interrupt enable bit for UARTn Data Register Empty
0
Interrupt from UDREn is inhibited (use polling)
1
When UDREn is set, request an interrupt
TXCIEn
Interrupt enable bit for Transmit Complete
0
Interrupt from TXCn is inhibited (use polling)
1
When TXCn is set, request an interrupt
RXCIEn
Interrupt enable bit for Receive Complete
0
Interrupt from RXCn is inhibited (use polling)
1
When RXCn is set, request an interrupt
WAKEIEn
Interrupt enable bit for Wake in STOP mode. When device is in stop mode, if RXDn
goes to LOW level an interrupt can be requested to wake-up system. At that time the
UDRIEn bit and UARTnST register value should be set to ‘0b’ and “00H”, respectively.
0
Interrupt from Wake is inhibited
1
When WAKEn is set, request an interrupt
TXEn
Enables the transmitter unit
0
Transmitter is disabled
1
Transmitter is enabled
RXEn
Enables the receiver unit
0
Receiver is disabled
1
Receiver is enabled
UARTnEN
Activate UARTn module by supplying clock. When one of TXEn and RXEn values is “1”,
the UARTnEN bit always set to “1”.
0
UARTn is disabled (clock is halted)
1
UARTn is enabled
U2Xn
This bit selects receiver sampling rate.
0
Normal operation
1
Double Speed operation

Abov MC97F60128 Specifications

General

Brand	Abov
Model	MC97F60128
Category	Microcontrollers
Language	English