Abov MC97F60128 - Page 329

329
MC97F60128
ABOV Semiconductor Co., Ltd.
DECCR (FADPCM Decoder Control Register) : 40B0H (XSFR)
7
6
5
4
3
2
1
0
DFEIE
DMIE
DFFF
DECEN
DIVS
DCEN
DCLKS1
DCLKS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
DFEIE
Decoder FIFO Empty Interrupt Enable
0
Disable
1
Enable
DMIE
Decoder Match Interrupt Enable
0
Disable
1
Enable
DFFF
Decoder FIFO Full Flag
0
Not decoder FIFO full
1
Decoder FIFO full
DECEN
Decoder Block Enable
0
Disable decoder block
1
Enable decoder block
DIVS
Decoder Initial Value Setting
0
No effect
1
Clear counter and set initial data for decoder (When write, automatically
cleared ‘0’ after being execution)
DCEN
Decoder Counting Enable
0
Disable counting operation
1
Enable counting operation
DCLKS[1:0]
Decoder Clock Select
DCLKS1
DCLKS0
Description
0
0
fx/16
0
1
fx/8
1
0
fx/4
1
1
fx/2