Intel MCS 51 User Manual

intel.
8XC51FXHARDWAREDESCRIPTION
Table 6. TCON: Timer/Counter Control Register
I
TCON Address = 88H
ResetValue = 0000 OOOOB
BitAddressable
I
TF1
TR1
TFO
TRO IE1 IT1
IEO
ITO
Bit 7 6 5
4
3 2 1
0
Symbol
Function
TF1
Timer1overflowFlag.SetbyhardwareonTimer/Counteroverflow.Clearedby
hardwerewhenproceseorvectorsto interruptroutine.
TR1
Timer1Runcontrolbit.Set/clearedbysoftwareto turnTimer/Counter1on/off.
TFO
TimerOoverflowFlag.SetbyhardwareonTimer/CounterOoverflow.Clearedby
hardwarewhenprocessorvectorstointerruptroutine.
TRO
TimerORuncontrolbit.Set/clearedbysoftwareto turnTimer/CounterOon/off.
IE1
Interrupt1flag.Setbyhardwarewhenexternalinterrupt1edgeisdetected
(transmittedor level-activated).Clearedwheninterruptprocessedonlyif transition-
activated.
IT1
Interrupt1Typecontrolbit.Set/clearedbysoftwareto specifyfallingedge/lowlevel
triggeredexternalinterrupt1.
IEO
InterruptOflag.SetbyhardwarewhenexternalinterruptOedgeisdetected
(transmittedorlevel-activated).Clearedwheninterruptprocessedonlyif transition-
activated.
ITO
InterruptOTypecontrolbit.Set/clearedbysoftwareto specifyfallingedge/lowlevel
triggeredexternalinterruptO.
x=Oor 1
270S53-S4
Figure 9. Timer/counter Oor 1 in Mode 1: 16-Bit Counter
MODE3
a timerfunction(countingmachinecycles)andtakes
over the use of TRl and TFl from Timer 1.Thus THO
Timer 1 in Mode 3 simply holds its count. The effect is now controls the Timer 1 interrupt.
the same as setting TR1 = O.
Mode 3 is provided for applications requiringan extra
Timer O in Mode 3 establishes TLOand THO as two
8-bit timer or counter. When Timer Ois in Mode 3,
separatecounters. Tlse logic for Mode 3 on Timer Ois
Timer 1can be turned on and off by switching it out of
she–m in Figure 11. TLOuseathe Timer Ocontrol bits:
and into its own Mode 3, or can still be used by the
C/T, GATE, TRO,INTO, and TFO.THOis locked into
serialport as a baud rate generator,or in any applica-
tion not requiring an interrupt.
5-14

Intel MCS 51 Specifications

General

Architecture	8-bit
Number of Instructions	111
Clock Speed	12 MHz
Register Size	8-bit
Internal RAM	128 bytes
Internal ROM	4 KB
External Memory	64 KB
I/O Pins	32
Timers	2
Serial Port	1
Interrupts	5
Operating Voltage	5V
UART	Yes
Program Memory	4 KB
RAM	128 bytes
Instruction Set	CISC

Summary

MCS® 51 Family of Microcontrollers Architectural Overview

THE MCS®-51 INSTRUCTION SET

Provides an overview of the MCS®-51 instruction set, optimized for 8-bit control applications.

Interrupt Structure

Overview of the 8051 interrupt structure, sources, and vectoring.

MCS® 51 Programmer’s Guide and Instruction Set

MCS®-51 INSTRUCTION SET

Provides a summary of the 8051 instruction set, including mnemonics and operands.

8051, 8052 and 80C51 Hardware Description

TIMER/COUNTERS

Describes Timer 0 and Timer 1, including operating modes and control registers.

8XC52/54/58 Hardware Description

8XC51FX Hardware Description

PORT STRUCTURES AND OPERATION

Details port structures, I/O configurations, and external memory access.

SERIAL INTERFACE

Covers serial port modes, framing error detection, and baud rate generation.

87C51GB Hardware Description

SPECIAL FUNCTION REGISTERS

Provides a map of the SFR space and their reset values.

I/O PORTS

TIMERS/COUNTERS

PROGRAMMABLE COUNTER ARRAY

SERIAL PORT

Details the serial port's modes, framing error detection, and baud rates.

INTERRUPTS

Covers interrupt sources, enable registers, and priority levels.

RESET

83C152 HARDWARE DESCRIPTION

GLOBAL SERIAL CHANNEL

DMA OPERATION

INTERRUPT STRUCTURE