Intel MCS 51 User Manual

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8XC51FXHARDWAREDESCRIPTION
The other way of terrnina
ting the Idle mode is with a
The signal at the RST pin clears the IDL bit directly
hardwarereset. Since the clock oscillator is still nm- snd asynchronously. At this time the CPU resumes
ning, the hardwareresetneeds to be held activeforonly program execution from where it left off; that is, at the
two machine cycles (24 oscillator periods) to complete
instruction following the one that invoked the Idle
the reset. Mode. As shown in Figure 26, two or three machine
cycles of programexecution may take place before the
II
2’7
T
STAL2 = xTAL1
1
I
Oac
+
%-l
I
CLOCS
INTERRUPT,
GEN.
1
DSERIAL PORT,
TIMER BLOCKS
Figure 28. Idle and Power Down Hardware
Table 23. PCON:Power Control ReQieter
PCON
Address= 87H
ResetValue = OOXXOOOOB
Not Bit Addressable
SMOD1SMODO
—
POF
GF1 GFO PD
IDL
I
Bit 7 6 5 4 3 2
1
0
Symbol Funotion
SMOD1
SMODO
—
POF
GF1
GFO
PD
IDL
NOTE
DoubleBaudratebit.Whensettoa 1andTimer1isusedtogeneratebaudrates,andthe
SerialPortisusedinmodes1,2, or3.
Whenset,Read/Writeaccessesto SCON.7areto theFEbit.Whenclear,Read/Write
accessesto SCON.7aretotheSMObit.
Notimplemented,reservedforfutureuee.*
Power Off Flag. Set by hardware on the rising edge of VCC. Set or cleared by software. This
flag allows deteetion of a power failure caused reset. V= must remain above 3V to retain
this bit.
General-purposeflagbit.
General-purposeflagbit.
PowerDownbit.SettingthisbitactivatesPowerDownoperation.
Idlemodebit.Settingthisbitactivatesidlemodesoperation.
If 1sarewrittento PDandIDLatthesametime,PDtakesprecedence.
*Uaer softwareshouldnotwrite la to unimplementedbits.These bitsmsy be usedinfuture8051 familyproductsto
invokenewfeaturea. In that ease, the reset or inactivevalue of the new tit willbe O,and ifa activevalus willbe 1.
The vslueread from a reservedbitis indeterminate
5-39

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English