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8XC51FX HARDWARE DESCRIPTION
internal reset algorithm takes control. On-chip hard-
ware inhibits access to the internal IUM during this
time, but acceas to the port pins is not inhibited. To
eliminate the possibility of unexpected outputs at the
port pins, the instructionfollowing the one that invokes
Idle should not be one that writes to a port pin or to
external Data RAM.
10.2 Power Down Mode
An
instruction that sets PCON.1 causes that to be the
last instruction executed before going into the Power
Down mode. In this mode the on-chip oscillator is
stopped. With the clock frozen, all functions are
stopped, but the on-chip RAM and Special Function
Registem areheld. The port pins output the values held
by their respectiveSFRS and ALE and PSEN output
lows. In Power Down Vcc can be reducedto as low as
2V. Caremust be taken,however, to ensurethat Va is
not reduced before Power Down is invoked.
The C51FX can exit Power Down with either a hard-
ware resetor externalinterrupt. Reset redefineaall the
SFRSbut doeanot changethe on-chip IUUkf.An exter-
nal interrupt allows both the SFRS and the on-chip
IUUU to retairstheir valuea.
To properlyterminate Power Down the resetor exter-
nal interrupt should not be executed before VCC is
restoredto its normal operatinglevel and must be held
active long enough for the oscillator to restartand sta-
bilize (normally leas than 10 maec).
——
With an externalintermpL INTOor INT1 must be en-
abled and configuredas level-sensitive. Holding the pin
low restartathe oscillator and bringing the pin back
high completes the exit. After the RETI instruction is
executed in the interrupt service routine, the next in-
struction will be the one following the instruction that
put the device in Power Down.
10.3 Power Off Flag
The
Power Off Flag (POP) located at PCON.4, is set
by hardware when VCCrises from Oto 5 Volts. POF
can rdsobe set or clearedby software. This allows the
user to distinguish betw$mta “cold start” reset and a
“warnsstart” reset.
A cold start reset is one that is coincident with Vcc
being turned onto the device after it was turned off. A
warm start
reset occurswhile VCCis still appliedto the
device and could be generated, for example, by a
Watchdog Timer or an exit from Power Down.
Immediately after reset, the user’s software can check
the atatus of the POF bit. POF = 1 would indicate a
cold atart. The software then clears POF and com-
mences its tasks. POF = O immediately after reset
would indicate a warm start.
Vcc must remain
above 3 volts for POF to retain a O.
11.0 EPROM VERSIONS
The
8XC51FX mea the Improved “Quick-Pulse” pr~
_gm ~gorithrn. ~- devices pro-at VPP
= 12.75~d V~ = 5.OV) using a series of five
100 ps PROO pulaeaper byte programmed.This re-
auhs its a total programmingtime of approximately 5
seconds for the 87C51FA’S8 Kbyt~ 10secondsfor the
87C51FB’S 16 Kbytes, and 20 seconds for the
87C51FC”S32 Kbytea.
Exposare to Light The EPROM window must be cov-
ered with an opaquelabel when the device is in opera-
tion. This is not so much to protect the EPROM array
from inadvertent erasure,but to protect the RAM and
other on-chip logic. Allowing light to impinge on the
silicon die while the device is operatingoan cause logi-
cal malfunction.
12.0 PROGRAM MEMORY LOCK
In some microcontroller applications, it is desirable
that the Program Memorybe secure from softwarepi-
racy. The C51FX has varyingdegreesof programpro-
tection depending on the device. Table 24 outlines the
lock schemes availablefor each device.
EmYPtion Array:within the EPROM/ROM is MSiu-
ray of encryptionbytesthatareinitially unprogrammed
(all l’s). For EPROM devi% the user can program
the encryption arrayto encryptthe programcode bytea
during EPROM verification. For ROM devices, the
user submits the encryptionarrayto be programm
ed by
the factory. If an encryption array is submitted, LB1
will also be programmedby the factory.The encryption
array is not available without the Leek Bit. Program
code verifkation is performedas usual, exceptthat each
code byte comes out exclusive-NOR’ed (XNOR) with
5-40
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