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87C51GB HARDWARE DESCRIPTION
1.0 INTRODUCTION TO THE
8XC51GB
The 8XC51GBisa highlyintegrated 8-bit microcm-
troller basedon the MCS@-51architecture.As a mem-
ber of the MCS-51family,the 8XC51GBis optimizcd
for controlapplications.Its keyfeaturesare an analog
to digitalconverterand twoprograrnma
ble counter ar-
rays (PC@ capableof measuringand generatingpulse
informationon ten 1/0 pins. Alsoincludedare an en-
hancedserialport for multi-processo
r communications,
a serial
expansion port, hardware watchdogtimer, os-
cillatorfaildetection,an up/down timer/counter and a
programlockschemefor the on-chipprogrammemory.
Sincethe 8XC51GBis CHMOS,it has two software
selectablereducedpowermodes:Idle Modeand Power
DownMode.
The 8XC51GBused the standard 8051instruction set
and is functionally compatible with the existing
MCS-51familyof products.
Thisdocumentpresentsa comprehensivedescriptionof
the on-chiphardware featuresofthe 8XC51GB.It be-
ginswitha discussionofhowthe memoryis organized,
followedbythe instructionset, and then discusseseach
of the peripheralslistedbelow.
● Six8-bitBidirectionalParallel Ports
● Three 16-bitTimer/Counters with
— OneUp/Down Timer/Counter
— Programmable ClockOutput
. Analogto Digital converter with
— 8 channels
— 8-bitresolution
— comparemode
ble CounterArrays with
● TwoProgramma
— Compare/Capture
— SoftwareTimer
— Highspeed output
— PulseWidth Modulator
— WatchdogTimer (PCA only)
. Full-DuplexProgranun
ableSerialPort with
— Framing Error Detection
—
AutomaticAddress Recognition
● SerialExpansionPort
—
fourprogrammablemcdes
— fourselectablefrequencies
. HardwareWatchdogTimer
● Reset
—
asynchronous
—
activelow
● OscillatorFail Detection
. Interrupt Structure with
— 15interrupt sourcea
—
Four prioritylevels
● Power-SavingModes
— Idle Mode
— PowerDownMode
The table belowsummarizes
the productnamesof the
various 8XC51GB products currently available.
Throughoutthis docmnen~the productswillgenerally
be referredto as the 8XC51GB.Figure 1showsa func-
tionalblockdiagramof the 8XC51GB.
2.0 MEMORY ORGANIZATION
All MCS-51deviceshave a separate addressspacefor
ProgramMemoryand Data Memory.Thelogicalsepa-
ration of Program and Data Memoryallowsthe Data
Memorytobeaccessedby8-bitaddresses,whichcanbe
morequicklystored and manipulatedbyan 8-bitCPU.
Nevertheless id-bit Data Memoryaddressescan also
be generated through the DPTR register. Up to
64Kbyteseach of externalProgramand Data Memory
can be addressed.
2.1 Program Memory
Program Memory can only be read, not written to.
There can be up to 64 Kbytes of Program Memory.
The read strobe for external Program Memoryis the
signalFSEN(ProgramStoreEnable).PSENisnot acti-
vatedfor internal program fetches.
If the~ (ExternalAwes) piniseomectedto V~, all
programfetchesare directed to externalmemory.For
the ROMISSSdevices,all~rogram fetchesmust be to
externalmemory.If the EA pin is connectedto VCC,
then programfetches greater than 8K are to external
addressesforthe8XC51GBproducts
On
the 87C51GBwith = connectedto VCGprogram
fetchesto addresses
OOOOHthroughIFFFH are to in-
ternal ROMyand fetches to addresses2(OOHthrough
FFFFH are to external memory.
2.2 Date Memory
The 8XC51GBimplements256bytes of on-chipdata
RAM.The memoryspaceis dividedinto three blocks,
6-3
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