i~e
87C51GB HARDWAREDESCRIPTION
Fetches from external Program Memoryalwaysuse a
16-bitaddreas.Accessesto externalData Memorycan
use either a 16-bitaddress (MOVX @ DPTR) or an
8-bitaddress(MOVX@Ri).
Whenevera l~bit addreasis used,the highbyte of the
addreascorneaout on Port Z where it is held for the
durationof the read or wsitecycle.The Port 2 drivers
use the strongpullupsduringthe entiretime that they
are emittingaddressbits that are 1s.Thisoccurswhen
the MOVX@DPTR instruction is executed.During
this time the Port 2 latch (the SpecialFunctionRegis-
ter) doeanot haveto contain 1s,and the contentsofthe
Port 2 SFR are not moditkd. If the external memory
cycleis not immediatelyfollowedby another external
memorycycle,the undisturbedcontentsof the Port 2
SFR willreappearin the next cycle.
If an 8-bit address is being used (MOVX@ Ri), the
contentsof the Port 2 SFR remainat the Port 2 pins
throughout the external memory cycle. In this case,
Port 2 pinscan be usedto pagethe externaldata mern-
Ory.
In eithercase,the lowbyteofthe addressis tirne-muM-
plexedwith the &ta byte on Port O.The ADDRESS/
DATA signaldrives both FETs in the Port Ooutput
buffera.Thus,in externalbusmodethe Port Opins are
not open-drain outputs and do not require extemrd
psdlupa. The ALE (Address Latch Enable) signal
shouldbe used to capturethe addressbyte into an ex-
ternal latch. The address byte is valid at the negative
transitionofALE.Then,in a writecycle,the data byte
to be written appearson Port Ojust beforeWR is acti-
vated,and remainsthere untilafter ~ is deactivated.
In a read cycle,the in
cominf@te is acceptedat Port O
just beforethe read strobe @D) is deactivated.
Duringanyaccesstoexternsdmemory,the CPU writes
OFFHto the Port Olatch (the SpecialFunctionRegis-
ter), thus obliteratingthe informationin the Port O
SFR. Also,a MOVPOinstructionmustnot take place
duringexternalmemoryawesses.
If the user writes to
Port Oduringan externalmemoryfetch,the incoming
codebyteis corrupted.Therefore,do not vnite to Port
Oif externalprogrammemoryis used.
ExternalProgramMernoIYis accessed
under two con-
ditions:
1.Wheneversignal= is bigh,or
2. Wheneverthe programcounter(PC)containsan ad-
dressgreater than IFFFH (8K).
Thisrequiresthat theROMlessversionshave= wired
to VgSto enablethe lowerSK of programbytesto be
fetchedfromexternalmemory.
When the CPU is executingout of external Program
Memory,all 8bits of Port 2 are dedicatedto an output
functionand may not be usedfor generalpurposeI/O.
Duringexternal program fetchesthey output the high
byteof the PC with the Port 2 driversusingthe strong
pullupsto emit bits that are 1s.
5.0 TIMER/COUNTERS
The
8XC51GBhas three Id-bitTimer/Counters: Tim-
er O,Timer 1, and Timer 2. Each consistsof two 8-bit
registers:THx and TLx with x = O,1,or 2. All three
can be configuredto operate either as timers or event
calnters.
In the Timerfimction,the TLx registeris incremented
everymachinecycle.Thus,youcan thinkofit as cOunt-
ingmachinecycles.Sincea machinecycleconsistsof 12
oscillatorperioda,the countrate is ~2 ofthe oscillator
frequency.
In the Counterfunction,the registeris incremented
in
responseto a l-to-Otransition at its correspondingex-
ternal input pin: TO,Tl, or T2. In this function, the
externalinputis sampledduringS5P2ofeverymachine
cycle.Whenthe samplesshowa highin onecycleand a
low in the next cycle, the count is incremented. The
newcountvalueappearsin the registerduring S3P1of
the cyclefollowingthe onein whichthe transition was
detected Sinceit takes 2 machinecycles(24 oscillator
periods)to recognizea l-to-Otransition,the maximum
countrate is V24ofthe oscillatorfrequency.There ue
no restrictionson the duty cycleof the external input
signaLbut to ensure that a givenlevet is sampled at
least once before it changes,it shouldbe held for at
leastonefull machinecycle.
TimerOand Timer 1havefour operatingmodes:
Mtie O: 13-bittimer
Mode1: id-bit timer
Mode2: 8-bitauto-reloadtimer
Mode3: Timer Oas two separate 8-bittimers
Also,its possibleto useTimer 1to generatebaud rates
Timer2 has three modesof operation:
Timer2 Capture
Timer2 Auto-Reload(up or downcounting),and
Timer2 as a Baud Rate Generator
5.1 Timer Oand Timer 1
TheTimer/Gunter fimctionis selectedbycontrol bits
C—TXin TMOD (Table 4). These two Timer/Coun-
ters havefour operatingmodes,whichare selected by
bit-pairs(MIL MOX)alsoin TMOD.ModeO,Mode 1,
and Mode 2 are the same for both Timer/Counters.
Mode3 operationis diKerentfor the two timers.
6-13
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