Intel MCS 51 User Manual

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87C51GBHARDWARE DESCRIPTION
flowsetsthe TF2bit and causeaOFFFFHto bereload-
ed into the timer registers.
The EXF2bit toggleawheneverTimer 2 overflowsor
underflows.Thisbit can be usedas a 17thbit ofresolu-
tion if desired.In this operatingmode,EXF2doesnot
generatean interrupt.
5.3 Programmable Clock Out
The 87C51GBhas a new feature. A 50% duty cvcle
Toconfigurethe Timer/Counter 2as a clockgenerator,
bit C—T2(in T2CON)must be clearedand bit T20E
$us~&M~~jof~ ~esetet~it TR2 (in T2CON) ako
The ClockOut frequencydependsonthe osdator fre-
quencyand the reload value of Timer2 capture regis-
ters (RCAP2H,RCAP2L)m shownin this equation:
ClockOut.
oscillatorFrequency
Frequency 4 x [65536– (Rc/4p2H, Rr&4p2L)]
clock can be programmedto comeout on P1.b. h
In the Clock Out mode, Timer 2 roll-overswill not
pin, besidesbeinga regular 1/0 pin,has two alternate
functions.It canbe programmed(1)to inputthe exter-
generatean interrupt. This is similarto whenit is used
nal clockfor Timer/Counter 2,or (2)to output a 50%
as a baud-rategenerator.It is possibleto useTimer 2 as
duty cycle clock ranging from 61 Hz to 4 MHz at a
a baud-rate generator and a clock generatorsimulta-
16MHz operatingfrequency.Figure15showsTimer 2
neously.Note+however, that the baud-rate and the
clock-outfrequencywillbe the same.
in clock-outmode.
-T--r+J
11
WI
1-
c“Bit EIEl I
P1.o
!
1>1
I
(12)
w
I
+2
I
1
1
I
~T&N%:N
T20E (T2M0D. t)
P1.1 [-l
(122)0
t
I
I
EX~N2
270897-17
Figure15.Timer2 inClook-OutMode
6-2o

Intel MCS 51 Specifications

General

Architecture	8-bit
Number of Instructions	111
Clock Speed	12 MHz
Register Size	8-bit
Internal RAM	128 bytes
Internal ROM	4 KB
External Memory	64 KB
I/O Pins	32
Timers	2
Serial Port	1
Interrupts	5
Operating Voltage	5V
UART	Yes
Program Memory	4 KB
RAM	128 bytes
Instruction Set	CISC

Summary

MCS® 51 Family of Microcontrollers Architectural Overview

THE MCS®-51 INSTRUCTION SET

Provides an overview of the MCS®-51 instruction set, optimized for 8-bit control applications.

Interrupt Structure

Overview of the 8051 interrupt structure, sources, and vectoring.

MCS® 51 Programmer’s Guide and Instruction Set

MCS®-51 INSTRUCTION SET

Provides a summary of the 8051 instruction set, including mnemonics and operands.

8051, 8052 and 80C51 Hardware Description

TIMER/COUNTERS

Describes Timer 0 and Timer 1, including operating modes and control registers.

8XC52/54/58 Hardware Description

8XC51FX Hardware Description

PORT STRUCTURES AND OPERATION

Details port structures, I/O configurations, and external memory access.

SERIAL INTERFACE

Covers serial port modes, framing error detection, and baud rate generation.

87C51GB Hardware Description

SPECIAL FUNCTION REGISTERS

Provides a map of the SFR space and their reset values.

I/O PORTS

TIMERS/COUNTERS

PROGRAMMABLE COUNTER ARRAY

SERIAL PORT

Details the serial port's modes, framing error detection, and baud rates.

INTERRUPTS

Covers interrupt sources, enable registers, and priority levels.

RESET

83C152 HARDWARE DESCRIPTION

GLOBAL SERIAL CHANNEL

DMA OPERATION

INTERRUPT STRUCTURE