Intel MCS 51 User Manual

intd.
87C51GB HARDWARE DESCRIPTION
Table15.PCAModuleModes(CCAPMnRegister)
-
ECOMnCAPPnCAPNnMATn
IOGn
PWMnECCFn
ModuleFunotion
x
o
0 0
0
0 0 0 No
omration
x
x
1
0 0
0 0 x
I&bit espture bya postive-sdgetriggeron CEXn
x
x
o
1
0
0
0 x
16-bit capturebya nagativa-edgetriggeronCEXn
x
x 1
1 0 0 0 x
16-bit capture byatransition on CEXn
x
1
0 0 1
0 0 x
16-bit Software Timer
x
1 0
0 1
1
0 x 16-bitHigh Spaad Output
x
1 0
0
1
x o x Watchdog Timer
X = Don’tCare
I I
u’”’’=’”
,
,
m
I
x
I
o
I
o
I
o ECCFn
n = O,1, 2, 3 w 4
CCAPMn MOOEREGIS7ER
x = C-motCare
270897-21
-. .- --- .- . .. - . . . .
rlgureIY. IWA m-m ~pmmamoae
The externalinput pinsCEXOthroush CEX4are aam- In the interrupt serviceroutine,the Id-biteeoturevalue
pledfora tram~tiori.Whena validtr&sition isdetected
(positiveand/or negative edge), hardware loads the
Id-bitvalueof the PCA timer (C!H,CL)into the mod-
ule’s captureregisters (CCAPnH, CCAPnL).The re-
sultingvaluein the capture registersreflects the PCA
timer valueat the time a transitionwasdetectedonthe
cExn pin.
Upott a capture, the module’sevent flag (CCFn) in
CCONisset,and an ittterrupt is fiaggedif the ECCFn
bit in the moderegister CCAPMnis set. Tbe PCA in-
terrupt willthen be generatedifit is enabled.Sincethe
bardwaredoesnot cleer an eventflag when the ittter-
rupt isvectoredto, the flagmustbe clearedinsoftware.
must be sav~ in FUW beforethe next .+ure ewent
oeeurs. A subsequentcapture on the same CEXn pin
willwrite over the first capture valuein CCAPnI-iand
CCAPnL.
The timeit takes to servicethis interrupt routine deter-
mines the resolutionof back-to-backeventa with the
same PCA module.To store two 8-bit registers and
clear the event flags takes at least 9 machine cycles.
That includes the all to the interrupt routine. At
12MH2,this routinewotddtake lessthan 10ps. How-
ever,dependingonthe frequencyandinterrupt latency,
the resolutionwillvary with each application.
6-28

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English