Intel MCS 51 User Manual

intel.
87C51GB HARDWARE DESCRIPTION
Each module has a mode register called CCAPMn
(n = O,1,2, 3, or 4) to select whichfunctionit will
7.3 PCACaptureMode
perform. The ECCFn bit enablesthe PCA interrupt
Bothpositiveandnegativetransitionsoentriggera cap-
when a module’sevent flag is set. The event tlags
ture withthePCA.Thisgivesthe PCAthe flexibilityto
(CCFn)are locatedin the CCON register and get set
measureperiods,pulsewidths,duty cycles+and phase
when a capture event, software timer, or high speed
differenceson up to five separate inputs. Setting the
output eventoccursfor a givenmodule.
CAPPn snd/or CAPNn bits in the CCAPMn mode
Each mcdulealso has a pair of 8-bitcompare/capture
register (’fable 14)selects the input trigger-positive
end/or negativetransition-for modulen. Referto Fig-
registers(CCAPnHand CCAPnL)associatedwith it.
m 19.
Theseregistersstore the time whena capture eventoc-
curredor whena compare
eventshouldoccur.For the
Table 15 shows the combinations of bits in the
PWMmode,the high byte register CCAPnHcontrols
CCAPMnregister that are valid and have a defined
the duty cycleof the waveform.
function.Invalidcombinationswillproduceundetined
results.
Table14.CCAPMn:PCAModulesCompare/CaptureRegisters
CCAPMnAddress CCAPMOODAH
ResetValue= XOOOOOOOB
(n = O-4) CCAPM1 ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
NotBitAddressable
I
—
ECOMn
CAPPn CAPNn
MATn TOGn PWMn
ECCFn
Bit 7
6
5 4 3
2
1 0
SymbolFunction
—
Notimplemented,reservedforfutureuse*.
ECOMnEnableComparator.ECOMn= 1enablesthecomparatorfunction.
CAPPn capturePositive,CAPPn= 1enablespositiveedgecapture.
CAPNnCaptureNegative,CAPNn= 1enablesnegativeedgecapture.
MATn Match.WhenMATn= 1,a matchofthePCAcounterwiththismodule’acompare/cspture
registercausestheCCFnbitinCCONtobsset,flagginganinterrupt.
TOGn Toggle.WhenTOGn= 1,amatchofthePCAcounterwiththismodule’scompare/cspture
registercausestheCEXnpintotoggle.
PWMn PulseWidthModulationMode.PWMn= 1enablestheCEXnpintobeusedasapulsewidth
modulatedoutput.
ECCFn EnableCCFinterrupt.Ensblescompare/captureflagCCFnintheCCONregistertogenerate
aninterrupt.
NOTE
●
User software should not write 1s to resarved bite.These bitemaybe used in future 8051 family products to invoke
new features. In that ceae,the reset or inactive value of the new bit will be O, and its aofive value will be 1. The value
read from a reasrvsd bit is indsterrninate.
6-27

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English