I
i~e
87C51GB HARDWARE DESCRIPTION
Mode 1: 10bits are transmitted(throughTXD) or re-
ceived(throughRXD):a start bit (0), 8 data bits (LSB
tirst), and a stop bit (l). On receive,the stop bit goes
into RB8in SCON.The bsud rate in Mode 1 is vari-
able:youcan use either Timer 1to generatebaud rates
and/or Timer2to generatebaudrates. Figure25shows
the mode 1 Data Frame.
I
Stati Bit
Stop Bit
270S97-27
I
Figure25.Mode1DataFrame
Mode2: 11bits are transmitted(throughTXD) or re-
ceived(throughRXD):a start bit (0), 8 data bits (LSB
first), a programmable9th data bit, and a stop bit (l).
OnT ransmit, the 9tb &ts bit (TB8in SCON)can be
assignedthe valueofOor 1.Or, for example,the parity
bit @ in the PSW)could be movedinto TB8. 011re-
ceive,the 9th data bit goesinto RB8 in SCON,while
the stopbit is ignored.(Thevalidityof the stopbit can
be checkedwith Framing Error Detection.)The baud
rate isprogrammableto either 1/32or 1/64the oscilla-
tor frequency.SeeFigure26.
I
Start Bit
I
stop Bn 1
I
Ninth &a Blt
270S97-2B
I
Figure26.Mode2DataFrame
Mode3: 11bits are transmitted (throughTXD) or re-
ceived(throughRXD):a start bit (0), 8 data bits (LSB
first),a programmab
Ie9th data bitand a stopbit (1).In
fact, Mode 3 is the same as Mode 2 in all respects
exceptthe baud rate. Thebaud rate in Mode3 is vti-
able:you can use Timer 1and/or Timer 2 to generate
baudrates. SeeFigure27.
II
00 I D1 I D2 I 03 I 04 I D5 j 0S I D7 I OS
Data Byte
! 1
‘1’1
Stat+
Bit
I St+ Bit
Ninth Data Bit
270S97-2S
Figure27.Mode3DataFrame
8.1 Framing Error Detection
FrainingError Detectionallowsthe serialport to check
forvalidstopbitsin modes1,2, or 3.A missingstopbit
canbe caused,for example by noiseon the serial lines,
or transmissionby two CPUSsimultaneously.
If a stopbit is missing,a Framing Error bit (FE) is set.
TheFE bit can becheckedin softwareafter eachrecep-
tion to detect communicationerrors. Once set, the FE
bitmustbe clearedin software.A validstopbit willnot
clear FE.
The FE bit is locatedin SCONand sham the samebit
addressas SMO.Controlbit SMODOin the PCONreg-
ister determineswhetherthe SMOor FE bit is amessed.
If SMODO= O,then accessesto SCON.7are to SMO.
If SMODO= 1,then accesses
to SCON.7are to FE.
8.2 MultiprocessorCommunications
Modes2 and3providea 9-bitmodeto facilitatemtdti-
processorcommunication.The 9th bit allowsthe con-
troller to distinguishbetweenaddress and data bytea.
The 9th bit is set to 1for addreasand set to Ofor data
bytes. When receiving,the 9th bit goeainto RB8 in
SCON.Whentransmitting,the ninth bit TB8 is set or
clearedin software.
Theaerialport can be prograrnmed such that whenthe
stopbit is receivedthe serialport interrupt willbe acti-
vatedonlyif the receivedbyteis an addressbyte (RB8
= 1).This featureis enabledby settingthe SM2bit in
SCON.A wayto usethis featurein mukiprocesaorsys-
tems is as follows.
Whenthe masterprocesao “ta blockof
r wantsto tranamr
data to one of severalslaves,it first sends out an ad-
dreasbytewhichidentifiesthe target slave.Remember,
an addreasbyte has its 9th bit set to 1, whereasa data
byte has its 9th bit set to O.All the slave processors
shouldhavetheir SM2bits set to 1so they willonlybe
interrupted by an addressbyte. In fac~ the 8XC51GB
has an Automatic AddressRecognition
feature which
allows only the addressedslave to be
interrupted. That
is,the addresscomparisoncecumin hardware,not sofi-
ware. (On the 8051serial po~ sn address byte inter-
rupts sll slsves for sn sddress comparison.)
The addressed slave then clears its SM2 bit and pre-
paresto receivethe data bytesthat willbe coming.The
other slaves are unaffectedby these data bytes. They
are stillwaitingto beaddreasedsincetheir SM2bits are
all set.
6-36
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