Intel MCS 51 User Manual

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87C51GB HARDWARE DESCRIPTION
12.2 TimerInterrupts
Tinter Oand Tinter 1 interruptsare generatedby TFO
and TF1 in registerTCON,whichare set bya rollover
itstheir respectiveTimer/Counterregisters;the excep
tion is Timer Oin Mode 3. Whena timer interrupt is
generated, the tlag that generatedit is clearedby the
on-chiphardware whenthe serviceroutine is vectored
to. Thesetimer interruptsare enabledby bits ETOand
ET1in the IE register.
Timer2 interrupt is generatedbythe logicalOR ofbits
TF2 and EXF2 in register T2CON. Neither of these
*is cl~~ by hardwarewh~ the servieeroutke is
vectored to. In fact, the serviceroutine may have to
determm“ e whethexit wasTF2or EXF2 that generated
the interrupt, and the bit will have to be cleared in
software.The Timer 2 interruptis enabledbythe ET2
bit in the IE register.
12.3 PCAInterrupt
The PCA interrupts are generatedbythe IogiealOR of
five event tlags (CCFn, CICFn) and the PCA timer
oveflow flag (CF, CF1) in the registers CCON and
ClCON. None of these tlags are cleared by hardware
whenthe seMce routine is vectoredto. Normallythe
serviceroutinewillhaveto determinewhichbit flagged
the interrupt and clear that bit in software.Thisallows
the user to definethe priority of servieingeach PCA
module.
ThePCAinterruptis enabledbybit ECin the 333regis-
ter. The PCA1 interrupt is enabledby bit EC1 in the
IEA register.In addition,the CF (CF1)flagand each
of the CCFn (CICFn) flags
mustalsobeindividually
enabledbybits ECF (13CFl)and ECCFn(ECICFn) in
registers
CMOD (CIMOD) and CCAPMn
(CICAPMn),respectively,in order forthat tlag to be
ableto causean interrupt.
12.4 SerialPortInterrupt
The serialport interrupt is generatedbythe logicalOR
of bits RI and TXits register SCON.Neither of these
tlagsis clearedby hardware whenthe servieeroutineis
veetoredto. The servieeroutine willnormallyhaveto
det
erminewhetherit was RI or TI that generatedthe
interrup~ and the bit will have to be cleared in sofi-
ware. The serial port interrupt is enabledby bit ES in
the IE register.
12.5 InterruptEnable
Each of theseinterrupt sourecscan be individuallyen-
abled or disabledby setting or clearinga bit in the
Interrupt Enable(3)3and IEA) registemas shownin
Table 22. Note that IE also containsa globaldisable
bit, EA. If EA is set (l), the interruptsare individually
enabkd or disabledby their correspondingbits in IE
and IEA. If EA is clear (0), all interruptsare disabled.
Figure33showsthe interrupt controlsystem.
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Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English