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87C51GB HARDWARE DESCRIPTION
Table24.InterruptPollingSequence
1 (Highest)
INTO
2
SEP
3
INT2
4
TimerO
5
PCAI
6
INT3
7
m
6
AfD
9
INT4
10
Timer1
11
PCA
12
INT5
13
PCA
14
Timer2
15 (Lowest)
INT6
Note
thatthe “miority within level”structure is OtdY
usedto resolves-tiul~eous requestsofthe sameprior-
ity level.
12.7 InterruptProcessing
The interrupt flags are sampledat S5P2of everymac-
hine cycle.The samplesare polledduring the follow-
ing machine cycle.The Timer 2 overflowinterrupt is
slightly dif%rent, ss described in the Interrupt Re-
sponseTime section. If one of the flags was in a set
conditionat S5P2of the precedingcycle+the polling
cyclewillfind it and the interrupt systemwill generate
so LCALLto the appropriateserviceroutine,provided
this hardwsre-
generatedLCALLis not blockedby any
of the followingconditions:
1.An interrupt of equal or higher priority levelis al-
resdy in progress.
2.The
current (polling)cycle is not the final cyclein
the executionof the instructionin progress.
3.The instructionin progressis RETI or any writeto
the IE or 1Pregisters.
Anyofthese three conditionswillblock the generation
of the LCALLto the interrupt serviceroutine. Condi-
tion 2 ensures that the instructionin progress will be
completedbeforevect*g to anyserviceroutine.Con-
dition 3 ensures that f the instruction in progressis
RETIoranywritetoIEor1P,thenat leastonemore
instructionwillbe executedbeforeany interrupt is vec-
tored to.
The pollingcycleis repeatedwith each machinecycle,
andthe valuespolledarethe valuesthat werepresentat
S5P2 of the previousmachine cycle. If the interrupt
flagfor a level-sensitiveexternalinterrupt is activebut
not beingrespondedto for oneof the aboveconditions
and is not still activewhen the blockingcondition is
removed the deniedinterruptwillnot be serviced. In
other word$ the fact that the interrupt f&gwas once
activebut not servicedis not remembered.Every poll-
ing cycleis new.
T’hepollingcycle/LCALLsequenceisillustratedin the
Interrupt ResponseTimingDisgrarn.
Note that if an interrupt of a higherprioritylevelgoes
activeprior to S5P2ofthe machinecyclelabeledC3 in
the diagram,then in accordancewiththe aboverulesit
will be vectoredto duringC5 and C6,without any in-
struction of the lowerpriorityroutinehavingbeenexe-
cuted. This is the fastest possibleresponse
when C2 is
the tinal cycle of an instructionother than RETI or
write IE or 1P.
Thus the pr
ocessoracknowledgesan interrupt request
by executinga hardware-generatedLCALLto the ap-
propriate servicing routine. The hardware-generated
LCALL pushes the contentsof the Program Counter
onto the stack (but it doesnot save the PSW) and re-
loads the PC with an address that depends on the
source of the interrupt being vectored to. Table 25
showsthe interrupt vectoraddresses.
Table25.InternmtVeotorAddresses
Interrupt
Interrupt Clearedby
Vector
Souroa RequestBite Hardware Addraae
m
IEO
No(level) OO03H
Yes(trans.)
I TimerO I TFO I Yes I OOOBH!
m
IE1
No(level) O013H
Yes(trans.)
Timer1
TF1
Yes OOIBH
SerialPortI
Rl,TI
No O023H
Timer2
TF2,EXF2
No O02BH
SEP SEPIF
No O04BH
INT2
IE2 Yes
O053H
INT3
IE3
Yes
O05BH
INT4
IE4 Yes
O063H
INT5
IE5
Yes
O06BH
I INT6 I
IE6
! Yes I O073H I
6-47
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