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87C51GBHARDWARE DESCRIPTION
Executionproceedsfrom that locationuntil the RETI
instruction is encountered.The RETI instruction in-
forms the processo
r that this interrupt routine is no
longerin progr~ thenpopsthe toptwobytmfrom the
stack end reloads the Program Counter.Executionof
the interrupted program continuesfrom where it left
off.
Note that a simple RET instructionwould also have
returned executionto the interrupted program,but it
would have I& the interrupt controlsystemthinking
interrupt wasstill in progress.
The starting addrrsses of consecutiveinterrupt service
routinesare only8 byteaapart. That meensif consecu-
tiveinterruptaare beingused (IEOand TFO,for examp-
le, or TFOandIE1),end ifthe firstinterruptroutineis
more than 7 bytes long,then that routinewillhave to
executea jump to someother memorylocationwhere
the serviceroutine can be completedwithout overlap
ping the stertingaddressof the nextinterrupt routine
12.8 InterruptResponseTime
The ~ end INT1 levelsare inverted and latched
into the Interrupt FlagsIEO,and IE1 at S5P2of every
machinecycle.The levelof interrupts2 through 6 are
also latched into the appropriate flags (IE2-IE6) in
S5P2.Similarly,the Timer 2 tlag EXF2 and the Serial
Port flagsRI and IT are set at S5P2.Thevaluesare not
actually polledby the circuitryuntil the next machine
cycle.
TheTimerOand Timer 1flags,TFOend TFl, are set at
S5P2of the cycle in which the timers overtlow. The
valuesarethen polledbythe circuitryin the next cycle.
However,the Timer 2 fisg TF2 is set at S2P2 and is
polledin the same cyclein whichthe timer overflows.
Ifa requestisactiveand conditionsare rightfor it to be
acknowledged,a hardware subroutinecell to the re-
questedserviceroutinewillbethe nextinstructionto be
executed.The call itselftekestwocycles.Thus, a mini-
mumofthree completemachinecycleselapsesbetween
activationof an external interrupt requestend the tre-
ginningof execution of the service routine’s first in-
struction.SeeFQure 34.
A longerresponse time wouldresult if the request is
blockedbyone of the 3 conditionsdiscussedin the In-
terrupt Proccesingsection.If en interrupt of equal or
higherprioritylevelis alreadyinprogress,the addition-
al wait time obviouslydependson the nature of the
other interrupt’s service routine. If the instruction in
progressisnot in its finalcycle,the additionalwait time
cannotbemorethan 3cycles,sincethe longestinstruc-
tions(MULand DIV) are only4 cycleslon~ and ifthe
instructionin progressisRETI or writeto IE or 1P,the
additionalweit time carmotbe more than 5 cycles (a
maximumof one or more cycleeto complete the in-
structionin progrewAplus4 cyclesto completethe next
instructionif the instructionis MULor DIV).
Thus,in a single-interruptsys~ the responsetime is
always more than 3cyclesandlessthan9 cycles.
l-t
e
INTERRUPT INTERRUPT
GOES
LATCHED
ACTIVE
This is the fastestpossible
.....
INTERRUPTS LONG CALLTO
INTERRUP7ROUNNE
ARE POLLED INTSRRUPT
VEC!TORAOORESS
270SS7-S4
responsewhenC2 is the finalcycle of an instructionother then RETI or writeIE or 1P.
Figure34.InterruptResponseliming Disgrsm
6-46
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