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87C51GB HARDWARE DESCRIPTION
13.0 RESET
The resetinput is the RESETpin,whichhas a Schmitt
Triggerinput. A reset is accomplishedby holdingthe
RESET pin low for at least two machine cycles (24
oscillator periods). On the 8XC51GB,reset is asyn-
chronousto the CPU clock.This meansthat the oacil-
Iatordoesnot haveto berunningforthe I/O pinsto be
in their resetcondition.However,VW has to bewithin
the specitiedoperatingconditions.
Once Reset has reached a high level, the 8XC51GB
mayremainin its reset state forupto 5machinecycles.
This is causedby the OFD circuitry.
Whilethe RESETpin is low,the port pins, ALE and
PSENare weaklypulledhigh.After RESETis pulled
~it ~ take Upto 5 machinecyclesfor ALE md
PSENto start clocking.For this reason,other devices
can not be synchronizedto the internaltimingsof the
8XC51GB.
Drivingthe ALE and PSEN pins to Owhile reaet is
activecouldcause the deviceto go into an indetermi-
nate state.
The internal reset algorithm redefines most of the
SFRS.Refer to individualSFRSfor their reset values.
The internal W is not affectedby reset. On power
up the RAM content is indeterminate.
13.1 Power-OnReset
For CHMOSdevices,whenVCCis turnedom an auto-
matic reset can be obtained by connecting the
RE3ET pin to V~ through a 1 pF capacitor. The
CHMOSdevicesdonot requirean externalresistor like
the HMOSdevicesbecausetheyhaveaninternal pullup
on the= pin. Figure35showsthis.
When power is turned on, the circuit holds the
RESETpinhighforan amountoftimethat dependson
the capacitorvalueand the rate at whichit charges.To
ensurea valid reset the RESETpin mustbe held low
longenoughto allowthe oscillatorto start up plustwo
machinecycles.
On power up, Vcc should rise within approximately
ten milhsec
onda.The oscillator start-up time will de-
pendontheoscillatorfrequency.For a 10MHz crystal,
thestart-uptime is typically1rns.For a 1MHzcrystal,
the start-up time is typically10ms.
Poweringup the device without a valid reset could
causethe CPU to start executinginstructionsfrom ass
indeterminatelocation.This is becausethe SFRS,spe-
oiticsllythe Program Counter, may not get properly
inidalized.
14.0 POWER-SAVINGMODES
For applicationswherepowerconsumptionis critic+d,
the 8XC51GBprovideatwo powerreducingmodesof
operation:Idle and Power Down.The input through
which backup power is supplied during these opera-
tions is VCC.The Idle and Power Down modesare
activatedby setting bits IDL and PD, respectively,in
the SFR PCON (Table26). Figure 36 showsthe Idle
and powerDown CirCUitry.
In the Idlemode(IDL = 1),the oscillatorcontinuesto
run and the InterrupL Serial Port, PCA, and Timer
blockscontinueto be clocked,but the clock signal is
gatedoffto the CPU. In PowerDown(PD = 1),the
oscillatoris frozen.
Vcc
a
ii5i
Vcc
+
1/br
8XC51GS
%s
Vss
27C$.97-35
Figure 35. Power-OnReeetCircuitry
6-49
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