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83C152 HARDWARE DESCRIPTION
2.1.1 SPECIAL FUNCTION REGISTERS (SFRS)
The following
list containsall the SW their names
and function.All of the SFRSof the 80C51BHare re-
tainedand for a detailedexplanationoftheir operation,
pleaserefer to the chapter, “Hardware Descriptionof
the 8051and 8052”that is found in the Embedded
ControllerHandbook.An overviewofthe newSFRSis
foundin Section2.1.1.1,with a detailedexplanationin
Section3.7, Section4.5,and 6.0.
2.1.1.1 New SFRS
The followingdescriptionsare quickoverviewsof the
newSFRS,and not intendedto givea completeunder-
standing of their use. The reader shouldrefer to the
detailed explanationin Section3 for the GSC SFRS,
and Section4 for the DMA SFRS.
ADR 0,1,2,3- (95H, OA5H,OB5H,OC5H)Contains
the fourbytesfor addressmatchingduringGSCopera-
tion.
AMSKO- (OD5H)selects “don’tcare” bits to be used
withADRO.
AMSK1- (OE5H)Selects“don’tcare” bits to be used
withADR1.
BAUD - (W-I) Containsthe prograrnma
ble valuefor
thebaudrate generatorfor the GSC.Thebaudrate will
equal(foac)/((BAW+ 1) X 8).
BCRLO- (OE2H)Containsthe low byte of a comrt-
downcounter that determines whenthe DMA access
for ChannelOis complete.
BCRHO- (OE3H)Contains the high byte for count-
downcounter for ChannelO.
BCRL1 - (OF2H)Same as BCRLOexceptfor DMA
Channel L
BCRH1 - (OF3H)Same as BCRHOexceptfor DMA
Channel 1.
BKOFF - (OC4H)An 8-bit count-downtimer used
with the CSMA/CD resolutionatgorithm.
DARLO- (OC2H)Containsthe lowbyteofthe destina-
tion address for DMA Channel0,
DARHO- (OC3H)Containsthe highbyte of the desti-
nationaddress for DMA channel O.
DARL1 - (OD2H)Sameas DARLOexceptfor DMA
Channel 1.
DARH1 - (OD3H)Sameas DARHOexceptfor DMA
Channel 1.
DCONO- (92H) Contains the Destination Address
Space bit (DAS), Increment Destination Address bit
(IDA), Source Addreas Space bit (SAS), Increment
Source Address bit (ISA), DMA Channel Mode bit
(DM), Transfer Mode bit (TM), DMA Done bit
(DONE), and the 00 bit (GO). DCONOis used to
control DMAChannelO.
DCONI - (93H) Same as DCONOexcept this is for
DMA Channel1.
GMOD - (84H) Contains the Protocol bit (PR), the
Preamble Mgth (PL1,O),CRC Type (CT), Addf-
Lersgth(AL),Modeselect(M1,O),and ExternalTrans-
mit Clock(TXc). This registeris usedfor GSCopera-
tion only.
IENI - (OC8H)Interrupt enableregisterfor DMA and
GSCilltt31111ptS.
IFS - (OA4H)Determinesthe numberofbit timessepa-
rating transmittedframes.
IPN1 - (OF8H)Interrupt priority register for DMA
and GSCinterrupts.
MYSLOT- (OF5H)Contains the Jamming mode bit
(DC.7),the Deterministic CollisionResolution Algo-
rithm bit (DCR), and the DCR slot address for the
GSC.
P4 - (oCOII)COntainsthe memory“image”of Port 4.
PRBS- (OE4H)Containsa pseudo-randomnumberto
be usedin CSMA/CDbackoffalgorithms.Maybe read
or writtento by user software.
RFIFO - (F4H)RFIFO is usedto accessa 3-byteFIFO
that containsthe receivedata from the GSC.
RSTAT - (OE8H)Contsins the Hardware Based Ac-
knowledgeEnablebit (HABEN), Global ReceiveEn-
able bit (GREN), Receive FIFO Not Empty bit
=), ReceiveDone bit (RDN), CRC Error bit
(CRCE), AlignmentError bit (AE), Receiver Colli-
sion/Abort detect bit (RCABT),and the overrun bit
(OVR),usedwithboth DMA and GSC.
SARLO- (OA2H)Containsthe low byte of the source
addressfor DMA transfers.
SARHO- (OA3H)Gmtsins the highbyteof the source
addressfor DMA transfers.
SARL1- (OB2H)Sameas SARLObut for DMA Chan-
nel 1.
SARH1-(oB3H)Sameas SARH1but forDMA Chan-
nel 1.
SLOTTM- (OB4H)Determinesthe lengthof the slot
time in CSMA/CD.
TCDCNT- (OD4H)Containsthe numberof collisions
in the current frame if usingCSMA/CD GSC.
7-5
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