Intel MCS 51 User Manual

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83C152 HARDWARE DESCRIPTION
Old(O)/New(N)
o
N
N
N
N
N
:
N
N
N
N
N
N
N
N
N
N
N
N
o
0
:
N
~
N
:
o
0
0
N
N
B
:
N
N
N
N
N
N
o
0
N
o
N
o
:
o
0
0
0
N
Name
A
ADRO
ADR1
ADR2
ADR3
AMSKO
AMSK1
B
BAUD
BCRLO
BCRHO
BCRL1
BCRH1
BKOFF
DARLO
DARHO
DARL1
DARH1
DCONO
DCON1
DPH
DPL
GMOD
IE
IEN1
IFS
1P
IPN1
MYSLOT
Po
P1
P2
P3
P4
P5
P6
PC(3N
PRBS
Psw
RFIFO
RSTAT
SARLO
SARHO
SARLI
SARH1
SBUF
SCON
SLOITM
SP
TCDCNT
TCON
TFIFO
THO
TH1
TLO
TL1
TMOD
TSTAT
Addr
OEOH
095H
OA5H
OB5H
OC5H
OD5H
OE5H
OFOH
094H
OE2H
OE3H
OF2H
OF3H
OC4H
OC2H
OC3H
OD2H
OD3H
092H
093H
083H
082H
084H
OA8H
OC8H
OA4H
OB8H
OF8H
OF5H
060H
090H
OAOH
OBOH
OCOH
091H
OAIH
087H
OE4H
ODOH
OF4H
OE8H
OA2H
OA3H
OB2H
OB3H
099H
098H
OB4H
081H
OD4H
088H
085H
08CH
08DH
08AH
08BH
089H
OD8H
Function
ACCUMULATOR
GSC MATCHADDRESS O
GSC MATCHADDRESS 1
GSC MATCHADDRESS2
GSCMATCHADDRESS3
GSCADDRESSMASKO
GSCADDRESSMASK 1
B REGISTER
GSC BAUDRATE
DMA BYTECOUNT O(LOW)
DMA BYTECOUNT O(HIGH)
DMA BYTECOUNT 1 (LOW)
DMA BYTECOUNT 1 (HIGH)
GSC BACKOFFTIMER
DMA DESTINATIONADDR O(LOW)
DMA DESTINATIONADDRO(HIGH)
DMA DESTINATIONADDR 1 (LOW)
DMA DESTINATIONADDR 1 (HIGH)
DMACONTROLO
DMACONTROL1
DATAPOINTER(HIGH)
DATAPOINTER(LOW)
GSC MODE
INTERRUPTENABLEREGISTERO
INTERRUPTENABLEREGISTER 1
GSC INTERFRAMESPACING
INTERRUPTPRIORITY REGISTERO
INTERRUPTPRIORITY REGISTER 1
GSCSLOTADDRESS
PORTO
PORT 1
PORT2
PORT3
PORT4
PORT 5
PORT6
POWERCONTROL
GSC PSEUDO-RANDOMSEQUENCE
PROGRAMSTATUS WORD
GSC RECEIVEBUFFER
RECEIVESTATUS (DMA & GSC)
DMASOURCEADDR O(LOW)
DMASOURCE ADDR O(HIGH)
DMASOURCEADDR 1 (LOW)
DMASOURCEADDR 1 (HIGH)
LOCALSERIALCHANNEL (LSC)BUFFER
LOCALSERIALCHANNEL (LSC)CONTROL
GSC
SLOTTIME
STACKPOINTER
GSCTRANSMIT COLLISIONCOUNTER
TIMER CONTROL
GSCTRANSMIT BUFFER
TIMER O(HIGH)
TIMER 1 (HIGH)
TIMER O(LOW)
TIMER 1 (LOW
TIMER MODE
TRANSMITSTATUS (DMA& GSC)
7-6

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English