Intel MCS 51 User Manual

83C152 HARDWARE DESCRIPTION
The sameconditionsapply for both the 80C51BHand
C152for a correct reaet pulse or “power-on”resetex-
cept that Reset is active low on the C152.Pleaserefer
to the 8051/52Hardware Description Chapter of the
Intel EmbeddedControllerHandbookfor an explana-
tion on how to provi& a proper power-onreset.Since
R-is activelowon the C152,the resistorshouldbe
tiedto VCCand the capacitor shouldbe tied to VSS.
Becausethe clockingon part of the GSC circuitryis
independentof thhrocesao
r clock, data may still be
transmittedandDEN activeforsometimeafter resetis
applied. The transmissionmay continue for a maxi-
mum of four machinecycles after reset is tirst pulled
low.AlthoughReset has to be held lowfor onlythree
machinecyclesto be recognizedbythe GSChardware,
all of the GSC circuitry may not be reset until four
machine cycleahave passed. If it is
importantin the
user application that all transmission and ~ be-
comes inactive at the end of a reset, then ~ will
have to be held low for a
minimumof four machine
cycles.
2.4 Ports 4,5 and 6
Ports 4, 5 and 6 operationis identicalto Ports 1-3on
the 80C51BH.Thedescriptionof port operationcanbe
foundin the 8051/52HardwareDescriptionChapterof
the Intel EmbeddedControllerHandbook.Ports5 and
6 existonlyonthe “3B”and “JD” versionofthe C152
and can eitherfimctionas standard 1/0 portsor canbe
contlguredso that program memory fetches are per-
formedwiththesetwoports.To configureports5and6
as standard I/O ports, EBEN is tied to a logiclow.
Whenin this configuration,ports 5 and 6 operationis
identical to that of port 4 except they are not bit ad-
dressable.To configureports 5 and 6 to fetchprogram
memory, EBEN is tied to a logic high. When using
ports 5 ~d 6 to fetch the program memory,the si~
EPSENB used to enable the external memorydevice
insteadofPSEN.Regardlessof whichportsareusedto
fetch programmemog, all data memog fetchesoccur
over ports Oand 2. The 80C152JBand 80C152JDare
availableas ROMleasdevicesonly.ALE is stillusedto
latch the address in all contlgurations.Table2.1sum-
marizesthe control signalsand howthe portsmay be
used.
2.5Timer/Counters
The 80C51BHand C152have the same pair of 16-bit
generalpurposetirner/cmmters. The user shouldrefer
to the Intel EmbeddedControllerHandbookwhichde-
scribes the timer/counters and their use. The user
shouldbear in mind,whenreadingthe Intel Embedded
ControllerHandbookthat the C152does not have the
third eventtimernamedTimer2, whichis in the 8052.
2.6 Package
The 83C152is packagedin a 48 pin DIP and a 68lead
PLCC. This differs from the 40 pin DIP and 44 pin
PLCCofthe 80C51BH.The largerpackageis required
to accommodatethe extra 8 bit I/O port (P4). Figures
2.5A, 2.5B and 2.5C show the packageaand the pin
names.
(GRXD) PI.oc 1
u
4a a v=
(GTXD) P1.1 c 2 47 3 P4.O
(m) P1.2C 3 46 3 P4.1
(We) P1.3C 4
45 3
P4.2
(m) P1.4C 5 44 3 P4.3
(me) P1.5 c 6
43 3
P4.4
(=A) P1.6C 7 42 3 P4.5
P1.7 c a 41 2 P4.6
R1’5rrc 9 40 3 P4.7
(RxD) P3.o c 10 39 3 m
(Txo) P3.1 E 11
38 Z ALE
(=) P3.2 r 12 :;:;:::;:J 37 J-N
(m) P3.3 c 13 36 Z P2.7 (A15)
(TO) P3.4C 14
35 3 P2.6 (A14)
(Tl) P3.5 E 15
34 ~ P2.5 (A13)
(WR) P3.6C 16
33 5 P2.4 (A12)
(m) P3.7 c 17
32 3
P2.3 (Al 1)
(A/W) PO.Oc 18
31 3
P2.2 (Al O)
(A/01) PO.1c 19
30 3 P2.1 (A9)
(A/02) PO.2c 20
29 3
P2.O (A8)
(A/D3) P0,3c 21
28 3
po.7 (A/D7)
XTAL2c 22 27 D po.s (A/06)
XTAL1c 23
26 J po.5 (A/D5)
v~~c 24 25 ~ PO.4 (A/04)
270427-5
-. - -. --- -. - .
Table 2.1 Program Memory Fetches
EBEN Ezi
Program — —
Fetch via
PSEN
EPSEN
Comments
o 0 PO.P2
Active
Inactive AddressesO-OFFFFH
o
1
N/A
N/A
N/A invalidCombination
1
0
P5, P6
Inactive
Active AddressesO-OFFFFH
1 1 P5, P6
Inactive
Active AddressesO-1 FFFH
Po, P2
Active
Inactive Addresses> 2000H
7-13

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English