int&
83C152HARDWARE DESCRIPTION
(line idle for two bit-times).One bit-timelater (which
marksthe midpointof the next bit cell),if there is still
no l-to-Otransition, a valid EOF is assumedand the
line idlebit (LNI in TSTAT)gets set.
However,if the assumedEOF flagis interruptedby a
l-to-Otransitionin the bit-timefollowingthe fmt miaa-
ing transition,a collisionis assumed.In that case the
GSC hardware recognizes the collisionto have oc-
curred within
1/2 to 5/8 bit-timeafter the unexpected
transition.
3.2.6
RESOLUTION OF COLLISIONS
Howthe GSCreapondsto a detectedcollisiondepends
on what it was doingat the time the collisionwas de-
tected.What it mightbe doingis eithertransmittingor
receivinga frsmq or it mightbe inactive.
GSC Inactive
The collisionis detected whether the GSCis active or
not. If the GSCis neither transmittingnor receivingat
the timethe collisionis detected,it takesno action un-
lessuser softwarehas selected the DeterministicColli-
sion Resolution(DCR) algorithm. If DCR has been
selected,the GSC will participate in the resolutional-
gorithm.
GSC
Receiving
If theGSCis
alreadyin the processofreceivinga frame
at the time the collisionis detected, its reaponsede-
pendson whether the first byte of the frame has been
transferred into RF3F0 yet or not. If that hasn’t oc-
curredjthe GSCsimplyaborts the reception,but takes
no otheractionunlessDCR has beenselected.If DCR
has been selected,the GSC participatesin the resolu-
tion algorithm.
If the reception has rdready progressedto the point
where a byte has been transferred to RFIFO by the
time the collisionis detected, the receiveris disabled
(GREN = O),and the ReceiveError Interrupt tlag
RCABT is set. If DCR has beerrselected, the GSC
participatesin the resolutionalgorithm.
Incomingbitstake 1/2 bit time to gettlom the GRXD
pin to the bit decoder.The bit deccder strips off the
preamble/BOFbits, andthe firstbit at%rBOFis sbift-
ed into a serial strip buffer.The length of the strip
buffer is equal to the number of bits in the selected
CRC. It is within this buffer that address recognition
takes place. If the address is recognizedas one for
which reception should proceed, then when the first
addressbitexitsthe stripbut% it is shiftedintoan 8-bit
shiftregister.Whenthe shiftregisteris fidl, its content
is transferredto RFIFO. That is the event that deter-
mineswhethera collisionsets RCABTor not.
GSC
Transmitting
If the GSC is in the processof transmittinga frameat
the time the collisionis detected it will in everycase
executeits jam/backoffprocedure.Its reponaebeyond
that dependson whetherthe first byteofthe framehas
beentransferredfromTFIFO to the output shift regis-
ter yetor not. That trarrsfertakesplaceat the beginning
ofthe first bit ofthe BOF;that is,2 bit-timesbeforethe
end of the prearnble/BOFsequence.
If the transfer from TFIFO hasn’t occumedye~ the
GSChardware willtry againto gainaccessto the line
after its baekofftime has expired.Up to 8 automatic
restartscanbe attempted.If the 8threstart is interrupt-
ed by yet snother collision,the transmitter is disabled
(TEN = O) and the Transmit Error Interrupt flag
TCDTis set.
If the trsnsfa from TFIFO occursbeforea collisionis
detected,the transmitter is disabled(TEN = O)and
the TCDTtlag is set.
The responseof the GSCto detectedcollisionsis sum-
marizedin Figure 3.4.
I
What the GSC waa doing
I
Reaponae
I
nothing None,unless DCR = 1.
If DCR = 1, beginDORcountdown.
Receivinga Frame, firat
None,unlessDCR = 1.
bytenotin RFIFO yet.
If DCR = 1, beginDCRcountdown.
Receivinga Frame, first
Set RCABT,clearGREN.
bytealreadyin RFIFO. If DCR = 1, beginDCRcountdown.
I
Transmittinga Frame,first
I
Executejam/backoff.
bvtestillin TFIFO Restartifcollisioncounts8.
I
Transmittinga Frame,first
Executejam/backoff.
bytealreadytaken fromTFIFO -SetTCDT, clearTEN.
Figure 3-4. Response to a Deteoted Collision. References to DCR and the DCR Countdown
Have to 00 with the Deterministic Collision Resolution Algorithm.
7-24
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