Intel MCS 51 - Page 318

intd.
83C152 HARDWARE DESCRIPTION
~ Input
I
,
1,
CPU Osc. Periods
1,
Clock 1
0,
Clock 2
1,
I
I
14
rm output
1
1
,
I
1,
II
It
1-
,2 Osc. ‘ 4 Osc. ,
Periods P*llOds
270427-40
Figure 4.9. Minimum~/~ Response Time
Inhibit Rsqusstsr’s
DMXRQ
DUA to XRAM
7r
~ Input
(P1.6)
(
SQ
Q1
m output
P
DQ +
(P1.5)
Q3
Clock 1
— DQ
>
QIA
>
Clock 1
Ciock 2
270427-41
Figure 4.10. Internal Logic of the Requester
(Clock 1 and Clock 2 are Shown in Figure 4.9)
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