Intel MCS 51 User Manual

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83C152 HARDWARE DESCRIPTION
4.3.4 INTERNAL LOGIC OF THE ARBITER
When the arbiter wantsto DMA the XRAM, it first
aetivateaDMXRQ.ThissignalpreventsQ2frombeing
The internallogicofthe arbiter is ahownin Figure4.8. set if it is not alreadyset. An output low from Q2 en-
In operationan input lowat HLD sets Q2if the arbi-
ablesthe arbiter to carry out its DMA to XRAM, and
ter’s internal signal DMXRQ is low. DMXRQ is the
maintainsan output highat HLDA. When the arbiter
arbiter’s“DMA to XRAM Request”. SettingQ2 aeti- completeaits DMA, the signal DMXRQ ~to O,
vates HLDA through Q3. Q2 being set also disables
whichenablesQ2toacceptsignalsfromthe HLDinput
any DMAsto XIU-M &at the arbikr mightdecideto again.
do duringthe requester’sDMA.
Figure
4.9 showsthe
minimumresponsetime, 4 to 7
CPU oscillator perioda, between a transition at the
HLD inputand the responseat HLDA.
Inhibit Arbiter’s
DMXRQ
OMA to XRAM
I
4
KD Input
(P1.5)
~ Da DO
D
Q1 Q2 Q3
> b
>
6 ~
WA
Output
(P1.6)
Clock1 Clock2
Clock1
270427-39
Figure
4.8. Internal Logic of the Arbiter
7-53

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English