Intel MCS 51 User Manual

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83C152HARDWARE DESCRIPTION
THl (08DH) - Timer 1 High byte, containsthe high
byte for timer/counter 1.
TI - Transxm“tInterrup~ see SCON.
TLO(08AH)- TimerOLowbyte,containsthe lowbyte
for timer/counter O.
TL1(08BH)- Timer 1Lowbyte,containsthe lowbyte
for timer/counter 1.
TM - TransferMod%see,DCONO.
TMOD(089H)
76543210
GATE
c/7 Ml MO GATE c/T Ml MO
TMOD.O(MO)- Mode selectorbit for TimerO.
TMOD.1(Ml) - Mode selectorbit for TimerO.
TMOD.2(Cm - Timer/Counter s.dectorbit for
TimerO.
TMOD.3(GATE) -
Gating Modebit forTimerO.
TMOD.4(MO)- Mode selectorbit for Timer 1.
TMOD.5(Ml) - Modeselectorbit for Timer 1.
TMOD.6(Cfi) - Timer/Counter selectorbit for
Timer 1.
TMOD.7(GATE) -
Gating Modebit for Timer 1.
TSTAT(OD8)- Transmi
t StatusRegister
76543210
LNI NOACK
UR TCDT TDN TFNF TEN DMA
TSTAT.O(DMA) - DMA Selwt - IfseL indicatesthat
DMAchannelsare usedto
semioetheGSCFIFO’sand
GSCinterruptaoccuron TDN and RDN,and also en-
ablesUR to becomeset. If cleared, indicatesthat the
GSCis operatingin it normal modeand interrupts oc-
cur on TFNE and RFNE.For more information on
DMA servicingplease refer to the DMA section on
DMA serialdemandmode(4.2.2.3).
TSTAT.1~N) - Transmit Enable- Whenset causes
TDN, w TCDT, and NOACK tlagsto be reset and
the TFIFO cleared.l%e transmitter willclear TEN af-
tera su ccesafd transmiasiottj a collision during the
da~ CRC,or endtlag.Ifclmred duringa transmission
the GSCtransmit pin goesto a steadystate highlevel.
This is the method usedto sendan abort chamcter in
SDLC.Also~ is forcedto a high level.The end of
transmissionowurs wheneverthe TFIFO is emptied.
TSTAT.2(TFNF) - Transmit FIFO not Ml - When
se~ indicates that new data may be written into the
transmitFIFO. The transmit FIFO is a three bytebuff-
er that loadsthe transmit shift register with data.
TSTAT.3(TDN) - T
ranamit Done - When set, indi-
catesthe successfulwmpletionofa frametransmission.
If HBAENis set, TDN willnot be set until the end of
the IFS followingthe transmitted message,sothat the
acknowledgecan be checked.If an acknowledgeis ex-
pectedand not rewiv~ TDN is not set. An acknowl-
edgeis notexpectedfollowinga broadcastor multi-cast
packet.
TSTAT.4(TCDT)- TransmitCollisionDetect -If set,
indicatesthat the transmitter halted due to a collision.
It is set ifa collisionoccursduringthe data or CRCor
if there are more than eightwlliaions.
T3TAT.5(tJR) - Underrun -
If set, indicates that in
DMA modethe last bit wasSW out of the transmit
:~~w~ad t$~t=m byte count did not equrd
owurs, the transrm“tterhalts
withoutsendingthe CRC or the end flag.
T3TAT.6(NOACK)- No Ackllow]edge- If set, indi-
catesthat noacknowledgewasreceivedfor the previous
frame. Will be set only if HBAEN is set and no ac-
knowledgeis received prior to the end of the IFS.
NOACK is not set followinga broadcast or a madti-
cast packet.
TSTAT.7(I-M) - Line Idle - If seGindicates the re-
ceivelineisidle.In SDLCprotocolit isset if 15consec-
utive ones are received.In C3MA/CD protocol, line
idleis setifGRx D remains
highfor approximately1.6
bit times.LNI is clearedafter a transition on GRx D.
TxC- ExternalClockinput for GSC transmitter.
UR - Underrunflag,seeTSTAT.
XRCLK- ExternalGSCReceiveClockEnablebi~see
PCON.
XTCLK - Extermd GSC Transmit Clock Enablebit,
seeGMOD.
7-70

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English