Intel MCS 51 User Manual

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83C152 HARDWARE DESCRIPTION
RSTAT.6(RCAB~ - ReceiverCollision/AbortDetect
- IfseL indicatesthat a collisionwasdetectedafter data
had been10wMinto the receiveFIFO in CSMA/CD
mode.In SDLCmodq RCABTindicatesthat 7consec-
utiveonesweredetectedprior to the endtlagbut after
data has keenloaded into the receiveFIFO. AE may
alsobe set if RCABTis set.
RSTAT.7(OVR)- Overrun - If set, indicatesthat the
receiveFIFO wasfull and new shift registerdata was
written into it. It is cleared by user software, AE
and/or CRCEmay also be set ifOVR is set.
SARHO(OA3H)- Source AddreasRegister High O,
containsthe highbyte of the sourceaddressfor DMA
ChannelO.
SARHI (OB3H)- Source Address Register High 1,
containsthe highbyte of the sourceaddressfor DMA
channel 1.
SARLO(OA2H)- SourceAddressRegisterLowO,con-
tains the low byte of the source address for DMA
ChannelO.
SARLI(OB2H)- SourceAddressRegisterLow 1,con-
tains the low byte of the source address for DMA
channel 1.
SAS- SourceAddressSpacebit, seeDCONO.
SBUF (099H) - Serial Buffer, both the receive and
transmit SFR locationfor the LSC.
SCON(098H)
7 6 5 4 3210
SMO
SM1 SM2 REN
TB8 \ RB8
TI I RI
SCON.O(RI) -
ReceiveInterrupt fiag.
SCON.1(TI) - Transmit Interrupt tlag.
SCON.2(RB8)- ReceiveBit 8, containsthe ninth bit
that was receivedin Modes2 and 3 or the stop bit in
Mode1if SM20.Not used in ModeO.
SCON.3
(TB8) - Tr
rmsmitBit 8, the ninth bit to be
transmittedin Modes2 and 3.
SCON.4(REm - Receiver Enable,enablesreception
for the I-SC.
SCON.5(SM2)- Enablesthe multiprocessorcommuni-
cationfeaturein Modes2 and 3 for the LSC.
SCON.6(SM1)- LSCmcde sptxirler.
SCON.7(SM2)- LSC modespeciiier.
SDLC- Standsfor SynchronousData LinkCmmmni-
cationand is a protocoldevelopedby IBM.
SLOTTM- (OB4H)Determin
es the lengthof the slot
time in CSMA/CD.
SP(081H)- Stack Pointer, an eightbit pointerregister
usedduringa PUSN POP, CALL,RET,or RETL
TCDCNT- (OD4H)Containsthe numberof collisions
in the currcn
t frame if usingprobabilisticCSMA/CD
and containsthe maximumnumberof slots in the de-
terministicmode.
TCDT - Transmit CollisionDetec~ seeTSTAT.
TCON(088H)
76543210
TF1 TR1 TFo
TRO IE1
IT1 IEO ITO
TCON.O(ITO)- Interrupt Omodecontrolbit.
TCON.1(IEO)- External interrupt Oedgetlag.
TCON.2(ITl) - Interrupt 1modecontrolbit.
TCON.3(IEl) - Externalinterrupt 1edgeflag.
TCON.4(TRO)- Timer Orun controlbit.
CON.5(TFO)- Timer Oovertlowflag.
TCON.6(TR1)- Timer 1 run controlbit.
TCON.7(TF1)- Timer 1over-tlowflag.
TDN - Transmit Done flag, w TSTAT.
TEN - Transmit Enablebit, seeTSTAT.
TFNF - Transmit FIFO Not Full tlag,seeTSTAT.
TFIFO - (85H)TFIFO is a 3-byteFIFO that contains
the transmissiondata for the GSC.
THO(08CH) - Timer OHigh byte containsthe high
bytefor timer/cmmter O.
7-69

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English