i~.
83C152 HARDWARE DESCRIPTION
PCON.5(REQ) - Requeatwmodebi~ set to a 1when
C152is to be operatedas the requester station during
DMA transfers.
PCON.6 (ARB) - Arbiter modebiL set to a 1 when
C152 is to be operated as the arbiter during DMA
transfers.
PCON.7(SMOD)- LSCmodebiL used to doublethe
baud rate on the LSC.
PDMAO- Priority bit for DMA ChannelOinterrupt,
seeIPN1.
PDMA1 - Priority bit for DMA Channel 1 interrupt,
see IPN1.
PGSRE- Prioritybit for GSCReceiveError interrupt,
seeIPN1.
PGSRV- Prioritybit for GSCReceiveValidinterrupt,
seeIPN1.
PGSTE - Priority bit for GSCTransmit Error inter-
rupt, see IPN1.
PGSTV- Priority bit for GSC Transmit Valid inter-
rupt, see IPN1.
PLO- One of two bits that determinesthe Preamble
Length,see GMOD.
PL1 - One of two bits that determhes the Preamble
Length,see GMOD.
PRBS- (OE4H)Pseudo-RandomBinarySequence,gen-
erates the pseudo-random number to be used in
CSMA/CD backoffalgorithms.
PS- Priority bit for the LSCserviceinterrupt see1P.
PTO- Priority bit for TimerOinterrupt, see 1P.
PTl - Priority bit for Timer 1interrupt, see1P.
PXO- Priority bit
for Externalinterrupt O, see 1P.
PX1 - Priority bit for Externatinterrupt 1,see 1P.
RCABT- GSC ReceiverAborterror bit, seeRSTAT.
RDN - GSCReceiverDonebi~see RSTAT.
GREN - GSC ReceiverEnablebi~ see RSTAT.
RFNE - GSC Receive FIFO Not Empty bit, see
RSTAT.
RI - LSCReeeiveInterrupt bit, seeSCON.
RFIFO - (F4H)RFIFO is a 3-byteFIFO that contains
the receivedata from the GSC.
RSTAT(OE8H)- ReceiveStatusRegister
7654321
0
IOVRIRCABTIAEICRCEIRDNIRFNEIGRENIHABENI
RSTAT.O(HBAEN) - Hardware BasedAcknowledge
Enable- If set, enablesthe hardware based acknowl-
edgefeature.
RSTAT.1(GRIN) - ReceiverEnable- When set, the
receiveris enabledto acceptincomingthsnea.The user
must clear RFIFO with sotlware before enablingthe
receiver.RFIFO is cleared by readingthe contents of
RFIFO untilRFNE = O.AftereachreadofRFIFO, it
takes onemachinecyclefor the status of RFNE to be
uxted. setting GREN
dSO CkUS RDN, CRCE,AE,
andRCABT.GREN isclearedbyhardwareat the end
ofa receptionor if any receiveerrors are detected.The
status of GREN has no effecton whetherthe receiver
detectsa collisionin CSMA/CD modeas the receiver
input circuitryalwaysmonitorsthe reeeivepin.
RSTAT.2(RFNE)- ReceiveFIFO Not Empty- If set,
indicatesthat the ree.eiveFIFO containsdata. The re-
ceiveFIFO isa three bytebufferintowhichthe receive
data is loaded.A CPU read of the FIFO retrievesthe
oldestdata and automaticallyupdatesthe FIFO point-
ers.SettingGREN to a onewillclearthereceiveFIFO.
Thestatus ofthis fig is ccmtrolledbythe GSC.Thisbit
is clearedif user softwareemptiesreceiveFIFO.
RSTAT.3(RDN) - ReceiveDone -If set, indicatesthe
succeastidcompletionofa receiveroperation.Willnot
be set if a CRC, alignment,abort, or FIFO overrun
error occurred.
RSTAT.4(CRCE)-CRC Error - Ifs@ indicatesthat a
properlyalignedframewasreceivedwitha mismatched
CRC.
RSTAT.5(AE) - Alignment Error - In CSMA/CD
mode,AE isset ifthe receivershiftregister(an internal
serial-to-parallelconverter)is not full and the CRC is
bad whenan EOF is detected.In C?WfA/CDthe EOF
is a line idle condition(see LNI) for two bit times. If
the CRC is correct while in CSMA/CD mode, AE is
not set and anyrnia-alignmentis assumedto be caused
by dribblebits as the line went idIe. In SDLC mode,
AE is set if a non-byte-alignedflagis received.CRCE
mayalsobe set. The setting of this flagis controlledby
the GSC.
7-68
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