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Intel MCS 51 User Manual

Intel MCS 51
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i~.
83C152 HARDWARE DESCRIPTION
IP.2 (PXl) - Assignsthe priorityof externrdinterrupt,
INT1.
IP.3 (PT1) - Assignsthe priorityof Timer 1interrupt,
T1.
IP.4 (I%) - Assignsthe priority of the LSC interrupt,
SBUF.
IPN1-(OF8~
76 5
4 3 2
1 0
I PGSTE I
PDMA1 ] PGSTV I PDMAO I PG.SF4EI PGSRV ]
Allowsthe user software twolewelsof prioritizationto
be assignedto each of the interruptsin IEN1. A 1as-
signsthe correspondinginterruptin IEN1 a higherin-
terrupt than an interrupt witha correspondingO.
IPN1.O(PGSRV)- Assignsthe priorityofGSCreceive
validinterrupt.
IPN1.1 (PGSRE) - Assignsthe priority of GSC error
receiveinterrupt.
IPN1.2(PDMAO)- Assignsthe priorityof DMA done
interrupt for ChannelO.
IPN1.3(PGSTV)- Assignsthe priorityof GSC trans-
mit validinterrupt.
IPN1.4(PDMA1)- Assignsthe priorityof DMA done
interrupt for Channel 1.
IPN1.5 (PGSTE)- Assignsthe priority of GSC trans-
mit error interrupt.
ISA- Increment SourceAddr~ see DCONO.
LNI - Line Idle see TSTAT.
LSC- LocalSerial Channel- Tbe asynchronousaerial
port foundon all MCS-51devices.Uses start/stop bits
and can transfer only 1byteat a time.
MO- Oneof two GSC modebits, seeTMOD.
Ml - One of two GSCmodebits, seeTMOD
MYSLOT-(OF5H)
76543210
—
DCJ I DCR
SA5 SA4
SA3 SA2 SA1
SAO
Determines which type of Jam is used, whichbackoff
algorithm is uaedj and the DCR slot address for the
GSC.
MYSLOT.0,1,2,3,4,5(SA0,1,2,3,4,5)- Thesebits deter-
minewhich slot address is assignedto the C152when
rrninisticbackoffduring CSMA/CD opera-
usingdete
tions on the GSC. Maximumslotsavailableis 63. h
addreasof OOHpreventsthat stationfrom participating
in the backoffprocess.
MYSLOT.6(DCR) - Determineswhichcollisionreso-
lutionalgorithmis used. If setto a 1,then the determi-
nistic backoffis
used.If cleared,then a random slot
assignmentis used.
MYSLOT.7(DCJ) - Determinesthe type of Jam used
during CSMA/CD operationwhena collisionoccurs.
If set to a 1 then a low D.C. levelis used as the jam
signal.If cleare&then CRC is used as the jam signal.
The jam is applied for a length of time equal to the
CRC length.
NOACK-No Acknowledgmenterror bit, seeTSTAT.
NRZI - Non-Return to Zero inverted,a type of data
encodingwhere a Ois representedby a changein the
levelof the serial link.A 1is representedbynochange.
OVR- @mrtlmerror bit, seeRSTAT.
PR - Protocolselectbit,seeGMOD.PCON(87H)
7654
3
2 10
SMODIARBI REQIGARENIXRCLK
GFIEN PD IDL[
PCON.O(IDL) - Idle bit, usedto place the C152into
the idle powersavingmode.
PCON.1 (PD) - Power Down bit, used to place the
C152into the powerdownpowersavingmode.
PCON.2 (GFIEN) - GSC Flag Idle Enable bit, when
set, enables idle flags (01111110)to be generatedbe-
tweentransm
itted framesin SDLCmode.
PCON.3(XRCLK)- ExternalReceive
Clockbit,used
to enablean externalclockto beusedforonlythere-
ceiverportionof the GSC.
PCON.4 (GAREN) - GSC AuxiliaryReceiveEnable
bi~ used to enable the GSC to receive back-to-back
SDLC frames. This bit has no tied in CSMA/CD
mode.
7-67

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Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

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