Intel MCS 51 User Manual

i@.
83C152 HARDWAREDESCRIPTION
transmit clock. The input clock is applied to P1.3
(T=). The user softwareia responsiblefor setting or
clearingthis flag.Extemrdreceiveclockis enabledby
setting PCON.3.
GO - DMA Go bi~ aceDCONO.
GRxD - GSCReceiveData input,an alternatefunction
of one ofthe port 1pins (PI.0). This pin is usedas the
receiveinput for the GSC. PLOmust be programmed
to a 1for this functionto operate.
GSC- GlobalSerialChannel- A high-level,multi-pro-
tccol, serial communicationcontroller added to the
80C51BHcore to accomplishhigh-speedtransfers of
packetizedserialdata.
GTxD - GSCTransmitData output,an alternatefunc-
tion of oneofthe port 1pins (P1.1).Thispinis usedas
the transmit output for the GSC. P1.1 must be pro-
_ed
to a 1 for this functionto operate.
HBAEN - HardwareBasedAcknowledgeEnable see
RSTAT.
HLDA - Hold Acknowledgean alternate functionof
one of the port 1pins (P1.6).This pin is used to per-
form the “HOLD ACKNOWLEDGE” function for
DMA transfers.HLDA can bean input or an output,
dependingon the configurationofthe DMA channels.
P1.6 must be programmedto a 1 for this functionto
operate.
HOLD - Hold,an alternate functionof oneofthe port
1pins(P1.5).Thispin is usedto performthe “HOLD”
functionforDMAtransfers.HOLD can bcan input or
an output,dependingonthe configurationofthe DMA
channels. P1.5 must be programnr
ed to a 1 for this
functionto operate.
IDA - IncrementDestinationAddress,see DCONO.
IE (OA8H)
7 654 3 2 1 0
EA
I ES I ETl EX1
ETo I EXO I
Interrupt EnableSFR,usedto individuallyenablethe
Timer and LocalSerial
Channelinterrupts. Alsocon-
tains the globalenablebit whichmuatbe set to a 1to
enableanyinterruptto be automaticallyrecognizedby
the CPU.
IE.O(EXO)- Embles the external interrupt ~ on
P3.2.
IE.2 (EM) - Enables the externalinterrupt INTI on
P3.3.
IE.3 (ETl) - Enablesthe Timer 1interrupt.
333.4(ES) - Enablesthe LocalSerialChannelintemrpt.
IE.7 (EA) - The globalinterrupt enable bit. This bit
mustbe set to a 1for anyotherinterrupt to be enabled.
IEN1-(OC8H)
76 5
4 3 2
1
0
Ill
EGSTE EDMA1 EGSTV
EDMAO
EGSRE EGSR
Inten-upt enable registerforDMAand GSCinterrupts.
A 1in any bit positionenablesthat interrupt.
IEN1.O(EGSRV)- Enablesthe GSCvalid receivein-
terrupt.
IEN1.1(EGSRE)- Enablesthe GSC rweive error in-
terrupt.
IEN1.2(EDMAO)- Enablesthe DMA done interrupt
for ChannelO.
IEN1.3(EGSIT()- Enablesthe GSCvalidtransmit in-
terrupt.
IEN1.4(EDMA1)- Enablesthe DMA done interrupt
for Chaunel 1.
lEN1.5(BGSTE)- Enablesthe GSCtransmit error in-
terrupt
IFS- (OA4H)InterframeSpace,detcrmineathe number
of bit times separatingtransmr
“ttedfi-atnesin Csw
CD and SDLC.
1P(OB8H)
7
654 3 2 i
o
Ps PTl
Pxl PTO
Pxo
Allows the user software two levels of prioritization to
be
assignedto each of the interruptsin IE.A 1assigns
the cmreapottdinginterrupt in
IE a higher interrupt
than an interrupt with a correspondingO.
IP.O(PXO)- Assignsthe priorityofexternal intermpL
INTO.
IP.1 (PTO)- Assignsthe priorityof Timer Ointcrrup~
To.
IE.1 (ETO)- Enablesthe Timer Ointerrupt.
7-66

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English