Intel Stratix 10 User Manual

h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
4.
Wait for tx_pma_ready/rx_pma_ready to deassert.
5. Read register 0xEE[7:4] to determine the actual refclk1 source.
6. Write register 0xEC[3:0] with the value from the previous step.
7. Reset the internal controller inside the PMA because the REFCLK source changed
by:
a. Write 0x200[7:0] = 0x00.
b. Write 0x201[7:0] = 0x00.
c. Write 0x202[7:0] = 0x00.
d. Write 0x203[7:0] = 0x81.
e. Poll 0x207[7] until it becomes 1. This indicates the internal controller is being
reset. Note the bit self-clears.
f. Read 0x204[0]. 0 indicates success.
8. Change TX/RX baud rate to refclk * 50 and above 15 Gbps by using PMA attribute
code 0x0005.
a. Write 0x84[7:0] = 0x32.
b. Write 0x85[7:0] = 0x80 (bit 7 applies the update to both TX/RX).
c. Write 0x86[7:0] = 0x05.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
9. Change serialization/deserialization factor to 40 bits wide by using PMA attribute
code 0x0014.
a. Write 0x84[7:0] = 0x33.
b. Write 0x85[7:0] =0x00.
c. Write 0x86[7:0] = 0x14.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
10. Change to internal or serial loopback mode by using PMA attribute code 0x0008.
a. Write 0x84[7:0] = 0x01.
b. Write 0x85[7:0] = 0x01.
c. Write 0x86[7:0] = 0x08.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English