Intel Stratix 10 - Page 142

f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
11. Enable PMA TX/RX clock path calibration upon enabling the PMA by using PMA
attribute code 0x0011.
a. Write 0x84[7:0] = 0x03.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x11.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
12. Enable the PMA by using PMA attribute code 0x0001.
a. Write 0x84[7:0] = 0x07.
b. Write 0x85[7:0] =0x00.
c. Write 0x86[7:0] = 0x01.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
13. Enable initial coarse adaptive equalization by using PMA attribute code 0x000A.
a. Write 0x84[7:0] = 0x01.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x0A.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
14.
Deassert tx_reset/rx_reset.
15. Disable internal or serial loopback mode by using PMA attribute code 0x0008.
a. Write 0x84[7:0] = 0x00.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x08.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1’b1.
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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