Intel Stratix 10

Figure 103. PMA Direct Datapath (Channels 0 to 11)
EHIP_LANE
x4
(10G /25G)
MAC + PCS
EHIP_LANE
x2
(10G /25G)
MAC + PCS
EHIP_LANE
x2
(10G /25G)
MAC + PCS
EHIP_LANE
x4
(10G /25G)
MAC + PCS
P
T
P
EHIP_CORE
(100G MAC
+ PCS)
EHIP_CORE
(100G MAC
+ PCS)
P
T
P
FEC
(528, 514) or
(544, 514)
(Aggregate:
100G)
(Fractured:
25G)
FEC
(528, 514)
(Fractured:
25G)
FEC
(528, 514)
or (544, 514)
(Aggregate:
100G)
(Fractured:
25G)
EHIP_TOP
EHIP_TOP
PMA Direct
PMA Direct
RS-FEC
Interconnect
Interconnect Interconnect
Interconnect
Interconnect
Interconnect
InterconnectInterconnectInterconnect
FPGA Core
11
10
9
8
7
6
5
4
3
2
1
0
RS-FEC
RS-FEC
PMA CH0
PMA CH1
PMA CH2
PMA CH3
PMA CH4
PMA CH5
PMA CH6
PMA CH7
PMA CH8
PMA CH9
PMA CH10
PMA CH11
10
108
1086
10 32
6
8
8
10
6
0 2
4
0 2
4
4
0 2
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
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