Intel Stratix 10 - Page 225

input wire [0:0] reconfig_clk, // reconfig_clk.clk
input wire [23:0] rx_serial_data, //
rx_serial_data.rx_serial_data
input wire [23:0] rx_serial_data_n, //
rx_serial_data_n.rx_serial_data_n
output wire [23:0] tx_serial_data, //
tx_serial_data.tx_serial_data
output wire [23:0] tx_serial_data_n //
tx_serial_data_n.tx_serial_data_n
) ;
wire[15:0] source ;
assign reset = ~source[0] ;
wire [23:0] rx_clkout, tx_clkout ;
nphy nphy (
.rsfec_avmm2_avmmread_in( ), // RSFEC_avmm2.read
.rsfec_avmm2_avmmrequest_in( ), // .waitrequest
.rsfec_avmm2_avmmwrite_in( ), // .write
.latency_sclk( 2'b0 ), // latency_sclk.latency_sclk
.pll_refclk0( pll_refclk0 ), // pll_refclk0.clk
.reconfig_write( ), // reconfig_avmm.write
.reconfig_read( ), // .read
.reconfig_address( ), // .address
.reconfig_writedata( ), // .writedata
.reconfig_readdata( ), // .readdata
.reconfig_waitrequest( ), // .waitrequest
.reconfig_clk( reconfig_clk ), // reconfig_clk.clk
.reconfig_reset( ~reset ), // reconfig_reset.reset
.reset( ~reset ), // reset.reset
.rx_clkout( rx_clkout ), // rx_clkout.clk
.rx_coreclkin( rx_clkout ), // rx_coreclkin.clk
.rx_dl_async_pulse( ), //
rx_dl_async_pulse.rx_dl_async_pulse
.rx_dl_measure_sel( ), //
rx_dl_measure_sel.rx_dl_measure_sel
.rx_is_lockedtodata( ), //
rx_is_lockedtodata.rx_is_lockedtodata
.rx_parallel_data( ), //
rx_parallel_data.rx_parallel_data
.rx_pma_ready( ), // rx_pma_ready.rx_pma_ready
.rx_ready( ), // rx_ready.rx_ready
.rx_serial_data( rx_serial_data ), //
rx_serial_data.rx_serial_data
.rx_serial_data_n( rx_serial_data_n ), //
rx_serial_data_n.rx_serial_data_n
.tx_clkout( tx_clkout ), // tx_clkout.clk
.tx_coreclkin( tx_clkout ), // tx_coreclkin.clk
.tx_dl_async_pulse( ), //
tx_dl_async_pulse.tx_dl_async_pulse
.tx_dl_measure_sel( ), //
tx_dl_measure_sel.tx_dl_measure_sel
.tx_parallel_data( {12{48'b0,32'h0f0f0f0f, 48'b0, 32'h0f0f0f0f}} ), //
tx_parallel_data.tx_parallel_data
.tx_pma_ready( ), // tx_pma_ready.tx_pma_ready
.tx_ready( ), // tx_ready.tx_ready
.tx_serial_data( tx_serial_data ), //
tx_serial_data.tx_serial_data
.tx_serial_data_n( tx_serial_data_n ) //
tx_serial_data_n.tx_serial_data_n
);
src src (
.probe( ), // probes.probe
.source( source ) // sources.source
);
B. PMA Direct PAM4 30 Gbps to 57.8 Gbps Implementation
UG-20056 | 2019.02.04
Send Feedback
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
225