Intel Stratix 10 User Manual

Table 18. RS-FEC Mode Configurations
Supported Mode RS-FEC
Code
Type
FEC Mode Alignment/Scrambling/
Transcoder Mode
Transcoder
Bypass
32GFC/ CPRI 24G (x1, x2, x3, x4) NRZ
(528,
514)
Fractured Fibre channel Not bypassed
128 GFC Aggregate Fibre channel Not bypassed
25GE FEC Direct (x1, x2, x3, x4) Fractured Basic Not bypassed
100 GbE Aggregate Basic Not bypassed
Interlaken PAM4
(544,
514)
Aggregate Fibre channel Bypassed
Figure 23. RS-FEC Options
Table 19. RS-FEC Parameters
Parameter Value Description
Enable aggregate mode On/Off
RS-FEC Clocking Mode EHIP clock
Clock 0
Clock 1
Clock 2
Clock 3
No Clock
Sets the clocking mode for the RS-FEC block. For some RS-
FEC topologies, the clock selection is fixed. In all other cases,
this control selects the TX adapter clock used to clock the
RS-FEC block.
First RS-FEC Lane first_lane0
first_lane1
first_lane2
first_lane3
Selects the first RS-FEC lane to be used. There are four lanes
in the RS-FEC block. When the RS-FEC block is in fractured
mode, any of the four lanes may be selected as the first lane.
For multiple channel Native PHY IP core instances with the
continued...
(3)
The Interlaken mode requires a special string in the quartus.ini file to enable its functionality.
For more details, contact My Intel support.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English