Intel Stratix 10 User Manual

Parameter Value Description
where 'n' is the log base 2 of the number of channels. Address
bits [18:0] provide the register offset address within the
reconfiguration space of the selected channel.
Enable Altera Debug Master
Endpoint
On/Off When enabled, the Native PHY includes an embedded Altera
Debug Master Endpoint (ADME) that connects internally to the
AVMM slave interface. The ADME accesses the reconfiguration
space of the transceiver and performs certain test and debug
functions via JTAG using the System Console. This option
requires you to enable the Share reconfiguration interface
option for configurations using more than one channel and may
also require that you include a jtag_debug link in the system.
Separate reconfig_waitrequest
from the status of AVMM
arbitration
On/Off
When enabled, the reconfig_waitrequest does not indicate
the status of AVMM arbitration. The AVMM arbitration status is
reflected in a soft status register bit. This feature requires that
you enable the Enable control and status registers feature
under Optional Reconfiguration Logic.
The default setting is Off.
Enable capability registers On/Off Enables capability registers, which provide high level
information about the transceiver configuration. Refer to the
PMA Capability Registers section.
Set user-defined IP identifier 0 Sets a user-defined numeric identifier that can be read from
the user_identifer offset when the capability registers are
enabled.
Enable control and status
registers
On/Off Enables soft registers for reading status signals and writing
control signals on the PHY interface through the embedded
debug. Refer to the PMA/PMA Interface AVMM Registers
section.
Configuration file prefix File prefix Specifies the file prefix to use for generated configuration files
when enabled. Each variant of the IP should use a unique prefix
for configuration files.
Generate SystemVerilog package
file
On/Off When enabled, The IP generates a SystemVerilog package file
named [Configuration file
prefix]_reconfig_parameters.sv containing parameters
defined with the attribute values needed for reconfiguration.
Generate C header file On/Off When enabled, The IP generates a C header file named
[Configuration file
prefix]_reconfig_parameters.h containing macros
defined with the attribute values needed for reconfiguration.
Generate MIF (Memory Initialize
File)
On/Off When enabled, the IP generates a Memory Initialization File
(MIF) named [Configuration file
prefix]_reconfig_parameters.mif. The MIF file contains
the attribute values needed for reconfiguration in a data
format. MIF streaming will be supported in future version of the
Intel Quartus Prime software.
Enable multiple reconfiguration
profiles
On/Off When enabled, you can use the GUI to store multiple
configurations. The IP generates reconfiguration files for all of
the stored profiles. The IP also checks your multiple
reconfiguration profiles for consistency to ensure you can
reconfigure between them.
Enable embedded reconfiguration
streamer
On/Off Enables the embedded reconfiguration streamer, which
automates the dynamic reconfiguration process between
multiple predefined configuration profiles.
Generate reduced reconfiguration
files
On/Off When enabled, the Native PHY generates reconfiguration report
files containing only the attributes or RAM data that are
different between the multiple configured profiles.
continued...
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Intel
®
Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English