Intel Stratix 10 User Manual

Note: Currently, only the PRBS31/PRBS31Q patterns are supported in internal or serial
loopback mode.
Figure 41. Internal or Serial Loopback Path
TX
Buffer
TX PMA
RX PMA
RX
Buffer
Loopback path
TX Data
Data Pattern
Generator
MUX
Serializer
TX EQ
RX EQ
Clock Recovery
Sampler
Data Pattern
Verifier
Deserializer
EHIP_LANE/
EHIP_CORE/
RS-FEC/
PMA Direct
Gray Encoder/
Pre-coder
NRZ/
PAM4
MUX
Gray/Pre-
decoding
NRZ/
PAM4
High Speed Clock
Error
Injector
Internal or serial loopback path
Legend:
For more details on Register Read/Write support and programming, refer to PMA
Register Map and PMA Attribute Codes to configure these parameters.
Related Information
• PMA Register Map on page 165
• PMA Attribute Codes on page 170
3.1.4.2. Reverse Parallel Loopback Path
The reverse parallel loopback path sets the transmitter buffer to transmit data fed
directly from the CDR recovered data.
When in reverse parallel loopback mode, the reference clock source of the received
data stream must be the same reference clock that the transceiver channel receives
(0ppm difference between the transmit and receive frequencies).
Additionally, the TX and RX bit rate/reference clock ratio and width mode register
settings must be set to the same value to ensure proper operation of the reverse
parallel loopback.
Using an external instrument, data is fed to the RX buffer, and the deserialized parallel
data stream of the receiver is looped back as the parallel data input stream for the
transmitter.
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English