UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 11 of 841
NXP Semiconductors
UM10360
Chapter 1: LPC176x/5x Introductory information
Debug related options:
• A JTAG debug interface is included.
• Serial Wire Debug is included. Serial Wire Debug allows debug operations using only
2 wires, simple trace functions can be added with a third wire.
• The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction
trace capabilities.
• The Data Watchpoint and Trace (DWT) unit is included. The DWT allows data
address or data value matches to be trace information or trigger other events. The
DWT includes 4 comparators and counters for certain internal events.
• An Instrumentation Trace Macrocell (ITM) is included. Software can write to the ITM in
order to send messages to the trace port.
• The Trace Port Interface Unit (TPIU) is included. The TPIU encodes and provides
trace information to the outside world. This can be on the Serial Wire Viewer pin or the
4-bit parallel trace port.
• A Flash Patch and Breakpoint (FPB) is included. The FPB can generate hardware
breakpoints and remap specific addresses in code space to SRAM as a temporary
method of altering non-volatile code. The FPB include 2 literal comparators and 6
instruction comparators.
1.8 On-chip flash memory system
The LPC176x/5x contains up to 512 kB of on-chip flash memory. A flash memory
accelerator maximizes performance for use with the two fast AHB-Lite buses. This
memory may be used for both code and data storage. Programming of the flash memory
may be accomplished in several ways. It may be programmed In System via the serial
port. The application program may also erase and/or program the flash while the
application is running, allowing a great degree of flexibility for data storage field firmware
upgrades, etc.
1.9 On-chip Static RAM
The LPC176x/5x contains up to 64 kB of on-chip static RAM memory. Up to 32 kB of
SRAM, accessible by the CPU and all three DMA controllers are on a higher-speed bus.
Devices containing more than 32 kB SRAM have two additional 16 kB SRAM blocks, each
situated on separate slave ports on the AHB multilayer matrix.
This architecture allows the possibility for CPU and DMA accesses to be separated in
such a way that there are few or no delays for the bus masters.
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