NXP Semiconductors LPC1769 - MII Mgmt Configuration Register (MCFG - 0 X5000 0020)

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User manual Rev. 3 — 19 December 2013 155 of 841
NXP Semiconductors
UM10360
Chapter 10: LPC176x/5x Ethernet
10.11.9 MII Mgmt Configuration Register (MCFG - 0x5000 0020)
The MII Mgmt Configuration register (MCFG) has an address of 0x5000 0020. The bit
definition of this register is shown in Table 138
.
Table 137. Test register (TEST - address 0x5000 ) bit description
Bit Symbol Function Reset
value
0 SHORTCUT PAUSE
QUANTA
This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. 0
1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a
PAUSE Receive Control frame with a nonzero pause time parameter was received.
0
2 TEST
BACKPRESSURE
Setting this bit will cause the MAC to assert backpressure on the link. Backpressure
causes preamble to be transmitted, raising carrier sense. A transmit packet from the
system will be sent during backpressure.
0
31:3 - Unused 0x0
Table 138. MII Mgmt Configuration register (MCFG - address 0x5000 0020) bit description
Bit Symbol Function Reset
value
0 SCAN INCREMENT Set this bit to cause the MII Management hardware to perform read cycles across a
range of PHYs. When set, the MII Management hardware will perform read cycles
from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow
continuous reads of the same PHY.
0
1 SUPPRESS
PREAMBLE
Set this bit to cause the MII Management hardware to perform read/write cycles
without the 32-bit preamble field. Clear this bit to cause normal cycles to be
performed. Some PHYs support suppressed preamble.
0
5:2 CLOCK SELECT This field is used by the clock divide logic in creating the MII Management Clock
(MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs
support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided
by the specified amount. Refer to Table 139
below for the definition of values for this
field.
0
14:6 - Unused 0x0
15 RESET MII MGMT This bit resets the MII Management hardware. 0
31:16 - Unused 0x0
Table 139. Clock select encoding
Clock Select Bit 5 Bit 4 Bit 3 Bit 2 Maximum AHB
clock supported
Host Clock divided by 4 0 0 0 x 10
Host Clock divided by 6 0 0 1 0 15
Host Clock divided by 8 0 0 1 1 20
Host Clock divided by 10 0 1 0 0 25
Host Clock divided by 14 0 1 0 1 35
Host Clock divided by 20 0 1 1 0 50
Host Clock divided by 28 0 1 1 1 70
Host Clock divided by 36 1 0 0 0 80
[1]
Host Clock divided by 40 1 0 0 1 90
[1]
Host Clock divided by 44 1 0 1 0 100
[1]