UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 541 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
If a channel’s HNF bit in the MCCAPCON register is set to enable “noise filtering”, a
selected edge on an MCI pin starts the dead-time counter for that channel, and the
capture event actions described below are delayed until the dead-time counter reaches 0.
This function is targeted specifically for performing three-phase brushless DC motor
control with Hall sensors.
A capture event on a channel (possibly delayed by HNF) causes the following:
• The current value of the TC is stored in the Capture register (CAP).
• If the channel’s capture event interrupt is enabled (see Table 463), the capture event
interrupt flag is set.
• If the channel’s RT bit is set in the MCCAPCON register, enabling reset on a capture
event, the input event has the same effect as matching the channel’s TC to its LIM
register. This includes resetting the TC and switching the MCO pin(s) in edge-aligned
mode as described in 25.7.6
and 25.8.1.
25.8.5 External event counting (Counter mode)
If a channel’s MODE bit is 1 in MCCNTCON, its TC is incremented by rising and/or falling
edge(s) (synchronously detected) on the MCI0-2 input(s), rather than by PCLK. The PWM
functions and capture functions are unaffected.
25.8.6 Three-phase DC mode
The three-phase DC mode is selected by setting the DCMODE bit in the MCCON register.
In this mode, the internal MCOA0 signal can be routed to any or all of the MCO outputs.
Each MCO output is masked by a bit in the current Commutation Pattern register MCCP. If
a bit in the MCCP register is 0, its output pin has the logic level for the passive state of
output MCOA0. The polarity of the off state is determined by the POLA0 bit.
All MCO outputs that have 1 bits in the MCCP register are controlled by the internal
MCOA0 signal.
The three MCOB output pins are inverted when the INVBDC bit is 1 in the MCCON
register. This feature accommodates bridge-drivers that have active-low inputs for the
low-side switches.
The MCCP register is implemented as a shadow register pair, so that changes to the
active commutation pattern occur at the beginning of a new PWM cycle. See 25.7.6
and
25.8.2
for more about writing and reading such registers.
Figure 126
shows sample waveforms of the MCO outputs in three-phase DC mode. Bits 1
and 3 in the MCCP register (corresponding to outputs MCOB1 and MCOB0) are set to 0
so that these outputs are masked and in the off state. Their logic level is determined by
the POLA0 bit (here, POLA0 = 0 so the passive state is logic LOW). The INVBDC bit is set
to 0 (logic level not inverted) so that the B output have the same polarity as the A outputs.
Note that this mode differs from other modes in that the MCOB outputs are not the
opposite of the MCOA outputs.
In the situation shown in Figure 126
, bits 0, 2, 4, and 5 in the MCCP register are set to 1.
That means that MCOA1 and both MCO outputs for channel 2 follow the MCOA0 signal.
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