UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 83 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)
The ISPR1 register allows setting the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Clearing the pending state
of interrupts is done through the ICPR0 and ICPR1 registers (Section 6.5.7
and
Section 6.5.8
).
Table 57. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)
Bit Name Function
0 ISP_PLL1 PLL1 (USB PLL) Interrupt Pending set.
Write: writing 0 has no effect, writing 1 changes the interrupt state to pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1 ISP_USBACT USB Activity Interrupt Pending set. See functional description for bit 0.
2 ISP_CANACT CAN Activity Interrupt Pending set. See functional description for bit 0.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
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