UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013  24 of 841
NXP Semiconductors
UM10360
Chapter 3: LPC176x/5x System control
3.6 External interrupt inputs
TheLPC176x/5x includes four External Interrupt Inputs as selectable pin functions. The 
logic of an individual external interrupt is represented in Figure 6
. In addition, external 
interrupts have the ability to wake up the CPU from Power-down mode. Refer to 
Section 4.8.8 “
Wake-up from Reduced Power Modes” for details.
 
Fig 6. External interrupt logic
Interrupt flag
(one bit of EXTINT)
write to EXTINTi
internal reset
EINTi to wakeup timer
EINTi pin
EXTMODEi
PCLK
to interrupt 
controller
EXTPOLARi
EINTi interrupt enable
PCLK
1
GLITCH 
FILTER
APB read 
of EXTINTi
Q
S
R
Q
S
R
Q
S
D
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