UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 585 of 841
NXP Semiconductors
UM10360
Chapter 30: LPC176x/5x Digital-to-Analog Converter (DAC)
30.4.3 D/A Converter Counter Value register (DACCNTVAL - 0x4008 C008)
This read/write register contains the reload value for the Interrupt/DMA counter.
30.5 Operation
30.5.1 DMA counter
When the counter enable bit CNT_ENA in DACCTRL is set, a 16-bit counter will begin
counting down, at the rate selected by PCLK_DAC (see Table 40
), from the value
programmed into the DACCNTVAL register. The counter is decremented Each time the
counter reaches zero, the counter will be reloaded by the value of DACCNTVAL and the
DMA request bit INT_DMA_REQ will be set in hardware.
Note that the contents of the DACCTRL and DACCNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.
30.5.2 Double buffering
Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set
in DACCTRL. In this case, any write to the DACR register will only load the pre-buffer,
which shares its register address with the DACR register. The DACR itself will be loaded
from the pre-buffer whenever the counter reaches zero and the DMA request is set. At the
same time the counter is reloaded with the COUNTVAL register value.
Reading the DACR register will only return the contents of the DACR register itself, not the
contents of the pre-buffer register.
Table 540. D/A Control register (DACCTRL - address 0x4008 C004) bit description
Bit Symbol Value Description Reset
Value
0 INT_DMA_REQ 0 This bit is cleared on any write to the DACR register. 0
1 This bit is set by hardware when the timer times out.
1 DBLBUF_ENA 0 DACR double-buffering is disabled. 0
1 When this bit and the CNT_ENA bit are both set, the double-buffering feature in the
DACR register will be enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next time-out of the counter.
2 CNT_ENA 0 Time-out counter operation is disabled. 0
1 Time-out counter operation is enabled.
3 DMA_ENA 0 DMA access is disabled. 0
1 DMA Burst Request Input 7 is enabled for the DAC (see Table 543
).
31:4 - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
Table 541: D/A Converter register (DACR - address 0x4008 C008) bit description
Bit Symbol Description Reset Value
15:0 VALUE 16-bit reload value for the DAC interrupt/DMA timer. 0
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