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User manual Rev. 3 — 20 December 2013 754 of 841
NXP Semiconductors
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Chapter 34: Appendix: Cortex-M3 user guide
34.3.4 Fault handling
Faults are a subset of the exceptions, see Section 34.3.3. The following generate a fault:
• a bus error on:
– an instruction fetch or vector table load
– a data access
• an internally-detected error such as an undefined instruction or an attempt to change
state with a
BX
instruction
• attempting to execute an instruction from a memory region marked as
Non-Executable (XN)
• an MPU fault because of a privilege violation or an attempt to access an unmanaged
region
34.3.4.1 Fault types
Table 641 shows the types of fault, the handler used for the fault, the corresponding fault
status register, and the register bit that indicates that the fault has occurred. See
Section 34.4.3.11 “
Configurable Fault Status Register” for more information about the fault
status registers.
[1] Occurs on an access to an XN region even if the MPU is disabled.
[2] Attempting to use an instruction set other than the Thumb instruction set.
Table 641. Faults
Fault Handler Bit name Fault status register
Bus error on a vector read Hard fault VECTTBL Section 34.4.3.12 “Hard Fault
Status Register”
Fault escalated to a hard fault FORCED
MPU mismatch: Memory
management
fault
--
on instruction access IACCVIOL
[1]
Section 34.4.3.13 “Memory
Management Fault Address
Register”
on data access DACCVIOL
during exception stacking MSTKERR
during exception unstacking MUNSKERR
Bus error: Bus fault - -
during exception stacking STKERR Section 34.4.3.14 “
Bus Fault
Address Register”
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
Attempt to access a coprocessor Usage fault NOCP Section 34.4.3.11.3 “
Usage Fault
Status Register”
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction set state
[2]
INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
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