UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 515 of 841
NXP Semiconductors
UM10360
Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
24.6 Register description
The PWM1 function includes registers as shown in Table 445 below.
Table 445. PWM1 register map
Generic
Name
Description Access Reset
Value
[1]
PWMn Register
Name & Address
IR Interrupt Register. The IR can be written to clear interrupts. The IR can be
read to identify which of eight possible interrupt sources are pending.
R/W 0 PWM1IR -
0x4001 8000
TCR Timer Control Register. The TCR is used to control the Timer Counter
functions. The Timer Counter can be disabled or reset through the TCR.
R/W 0 PWM1TCR -
0x4001 8004
TC Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK.
The TC is controlled through the TCR.
R/W 0 PWM1TC -
0x4001 8008
PR Prescale Register. The TC is incremented every PR+1 cycles of PCLK. R/W 0 PWM1PR -
0x4001 800C
PC Prescale Counter. The 32-bit PC is a counter which is incremented to the
value stored in PR. When the value in PR is reached, the TC is
incremented. The PC is observable and controllable through the bus
interface.
R/W 0 PWM1PC -
0x4001 8010
MCR Match Control Register. The MCR is used to control if an interrupt is
generated and if the TC is reset when a Match occurs.
R/W 0 PWM1MCR -
0x4001 8014
MR0 Match Register 0. MR0 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC sets any PWM output
that is in single-edge mode, and sets PWM1 if it’s in double-edge mode.
R/W 0 PWM1MR0 -
0x4001 8018
MR1 Match Register 1. MR1 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM1 in either
edge mode, and sets PWM2 if it’s in double-edge mode.
R/W 0 PWM1MR1 -
0x4001 801C
MR2 Match Register 2. MR2 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM2 in either
edge mode, and sets PWM3 if it’s in double-edge mode.
R/W 0 PWM1MR2 -
0x4001 8020
MR3 Match Register 3. MR3 can be enabled in the MCR to reset the TC, stop
both the TC and PC, and/or generate an interrupt when it matches the TC.
In addition, a match between this value and the TC clears PWM3 in either
edge mode, and sets PWM4 if it’s in double-edge mode.
R/W 0 PWM1MR3 -
0x4001 8024
CCR Capture Control Register. The CCR controls which edges of the capture
inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place.
R/W 0 PWM1CCR -
0x4001 8028
CR0 Capture Register 0. CR0 is loaded with the value of the TC when there is
an event on the CAPn.0 input.
RO 0 PWM1CR0 -
0x4001 802C
CR1 Capture Register 1. See CR0 description. RO 0 PWM1CR1 -
0x4001 8030
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