NXP Semiconductors LPC1769 - Cortex-M3 Processor Features and Benefits Summary; Cortex-M3 Core Peripherals

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User manual Rev. 3 — 20 December 2013 648 of 841
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Chapter 34: Appendix: Cortex-M3 user guide
LPC176x/5x devices support JTAG and Serial Wire Debug, Serial Wire Viewer, and
include the Embedded Trace Macrocell. See Section 33.1
for additional information.
34.1.1.3 Cortex-M3 processor features and benefits summary
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
• fast code execution permits slower processor clock or increases sleep mode time
• hardware division and fast multiplier
• deterministic, high-performance interrupt handling for time-critical applications
• optional memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
34.1.1.4 Cortex-M3 core peripherals
These are:
• Nested Vectored Interrupt Controller
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt
controller that supports low latency interrupt processing.
• System control block
The System control block (SCB) is the programmers model interface to the
processor. It provides system implementation information and system control,
including configuration, control, and reporting of system exceptions.
• System timer
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time
Operating System (RTOS) tick timer or as a simple counter.
• Memory protection unit
The Memory protection unit (MPU) improves system reliability by defining the
memory attributes for different memory regions. It provides up to eight different
regions, and an optional predefined background region.