UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 87 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)
The IABR1 register is a read-only register that allows reading the active state of the
second group of peripheral interrupts. This allows determining which peripherals are
asserting an interrupt to the NVIC, and may also be pending if they are enabled.
Table 61. Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304)
Bit Name Function
0 IAB_PLL1 PLL1 (USB PLL) Interrupt Active.
Read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active.
1 IAB_USBACT USB Activity Interrupt Active. See functional description for bit 0.
2 IAB_CANACT CAN Activity Interrupt Active. See functional description for bit 0.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
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