NXP Semiconductors LPC1769 - Sspn Raw Interrupt Status Register (SSP0 RIS -; Sspn Masked Interrupt Status Register (SSP0 MIS - 0 X4008 801 C, SSP1 MIS - 0 X4003 001 C)

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User manual Rev. 3 — 19 December 2013 426 of 841
NXP Semiconductors
UM10360
Chapter 18: LPC176x/5x SSP0/1
18.6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0x4008 8018,
SSP1RIS - 0x4003 0018)
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the SSPnIMSC.
18.6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0x4008 801C,
SSP1MIS - 0x4003 001C)
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the SSPnIMSC. When an SSP interrupt occurs, the interrupt service routine
should read this register to determine the cause(s) of the interrupt.
Table 375: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4008 8014,
SSP1IMSC - 0x4003 0014) bit description
Bit Symbol Description Reset
Value
0 RORIM Software should set this bit to enable interrupt when a Receive Overrun
occurs, that is, when the Rx FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
0
1 RTIM Software should set this bit to enable interrupt when a Receive Time-out
condition occurs. A Receive Time-out occurs when the Rx FIFO is not
empty, and no has not been read for a "time-out period". The time-out
period is the same for master and slave modes and is determined by the
SSP bit rate: 32 bits at PCLK / (CPSDVSR
 [SCR+1]).
0
2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
0
3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
0
31:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 376: SSPn Raw Interrupt Status register (SSP0RIS - address 0x4008 8018, SSP1RIS -
0x4003 0018) bit description
Bit Symbol Description Reset
Value
0 RORRIS This bit is 1 if another frame was completely received while the RxFIFO
was full. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
0
1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a
"time-out period". The time-out period is the same for master and slave
modes and is determined by the SSP bit rate: 32 bits at PCLK /
(CPSDVSR
 [SCR+1]).
0
2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 0
3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 1
31:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA