NXP Semiconductors LPC1769 - Exception Mask Registers

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User manual Rev. 3 — 20 December 2013 734 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
Interruptible-continuable instructions: When an interrupt occurs during the execution
of an
LDM or STM instruction, the processor:
After servicing the interrupt, the processor:
• stops the load multiple or store multiple instruction operation temporarily.
• stores the next register operand in the multiple operation to EPSR bits[15:12].
• returns to the register pointed to by bits[15:12].
• resumes execution of the multiple load or store instruction.
When the EPSR holds ICI execution state, bits[26:25,11:10] are zero.
If-Then block: The If-Then block contains up to four instructions following a 16-bit
IT
instruction. Each instruction in the block is conditional. The conditions for the instructions
are either all the same, or some can be the inverse of others. See Section 34.2.9.3 “
IT” for
more information.
34.3.1.3.6 Exception mask registers
The exception mask registers disable the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks.
To access the exception mask registers use the
MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK or FAULTMASK. See Section 34.2.10.6
“MRS”, Section 34.2.10.7 “MSR”, and Section 34.2.10.2 “CPS” for more information.
Priority Mask Register: The PRIMASK register prevents activation of all exceptions with
configurable priority. See the register summary in Table 626
for its attributes. The bit
assignments are shown in Table 631
.
Fault Mask Register: The FAULTMASK register prevents activation of all exceptions
except for Non-Maskable Interrupt (NMI). See the register summary in Table 626
for its
attributes. The bit assignments are shown in Table 632
.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except
the NMI handler.
Base Priority Mask Register: The BASEPRI register defines the minimum priority for
exception processing. When BASEPRI is set to a nonzero value, it prevents the activation
of all exceptions with same or lower priority level as the BASEPRI value. See the register
summary in Table 626
for its attributes. The bit assignments are shown in Table 633.
Table 631. PRIMASK register bit assignments
Bits Name Function
[31:1] - Reserved
[0] PRIMASK 0 = no effect
1 = prevents the activation of all exceptions with configurable priority.
Table 632. FAULTMASK register bit assignments
Bits Name Function
[31:1] - Reserved
[0] FAULTMASK 0 = no effect
1 = prevents the activation of all exceptions except for NMI.