NXP Semiconductors LPC1769 - System Handler Priority Registers

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User manual Rev. 3 — 20 December 2013 775 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.4.3.9 System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 31 of the exception handlers that
have configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 654
for their
attributes.
The system fault handlers and the priority field and register for each handler are:
Table 662. CCR bit assignments
Bits Name Function
[31:10] - Reserved.
[9] STKALIGN Indicates stack alignment on exception entry:
0 = 4-byte aligned
1 = 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to
indicate the stack alignment. On return from the exception it uses this
stacked bit to restore the correct stack alignment.
[8] BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data bus faults caused
by load and store instructions. This applies to the hard fault, NMI, and
FAULTMASK escalated handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused
by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe
memory. The normal use of this bit is to probe system devices and
bridges to detect control path problems and fix them.
[7:5] - Reserved.
[4] DIV_0_TRP Enables faulting or halting when the processor executes an
SDIV or UDIV
instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
[3] UNALIGN_T
RP
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses
1 = trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned
LDM , STM , LDRD , and STRD instructions always fault irrespective
of whether UNALIGN_TRP is set to 1.
[2] - Reserved.
[1] USERSETM
PEND
Enables unprivileged software access to the STIR, see Table 652
:
0 = disable
1 = enable.
[0] NONEBASE
THRDENA
Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of
an EXC_RETURN value, see Section 34.3.3.7.2 “
Exception return”.