UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 79 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)
The ISER1 register allows enabling the second group of peripheral interrupts, or for
reading the enabled state of those interrupts. Disabling interrupts is done through the
ICER0 and ICER1 registers (Section 6.5.3
and Section 6.5.4).
Table 53. Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104)
Bit Name Function
0 ISE_PLL1 PLL1 (USB PLL) Interrupt Enable.
Write: writing 0 has no effect, writing 1 enables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
1 ISE_USBACT USB Activity Interrupt Enable. See functional description for bit 0.
2 ISE_CANACT CAN Activity Interrupt Enable. See functional description for bit 0.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
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