UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 816 of 841
NXP Semiconductors
UM10360
Chapter 35: Supplementary information
35.4 Figures
Fig 1. LPC1768 simplified block diagram. . . . . . . . . . . . .9
Fig 2. LPC1768 block diagram, CPU and buses . . . . . .12
Fig 3. LPC176x/5x system memory map. . . . . . . . . . . .14
Fig 4. Reset block diagram including the wake-up timer20
Fig 5. Example of start-up after reset. . . . . . . . . . . . . . .21
Fig 6. External interrupt logic. . . . . . . . . . . . . . . . . . . . .24
Fig 7. Clock generation for the LPC176x/5x . . . . . . . . .30
Fig 8. Oscillator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for C
X1
/
X2
evaluation33
Fig 9. PLL0 block diagram. . . . . . . . . . . . . . . . . . . . . . .37
Fig 10. PLL1 block diagram. . . . . . . . . . . . . . . . . . . . . . .49
Fig 11. PLLs and clock dividers. . . . . . . . . . . . . . . . . . . .55
Fig 12. CLKOUT selection. . . . . . . . . . . . . . . . . . . . . . . .67
Fig 13. Simplified block diagram of the flash accelerator
showing potential bus connections . . . . . . . . . . .69
Fig 14. LPC176x LQFP100 pin configuration . . . . . . . . .92
Fig 15. LPC175x LQFP80 pin configuration . . . . . . . . . .92
Fig 16. Pin configuration TFBGA100 package. . . . . . . . .93
Fig 17. Ethernet block diagram . . . . . . . . . . . . . . . . . . .144
Fig 18. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .146
Fig 19. Receive descriptor memory layout. . . . . . . . . . .173
Fig 20. Transmit descriptor memory layout . . . . . . . . . .176
Fig 21. Transmit example memory and registers. . . . . .187
Fig 22. Receive Example Memory and Registers . . . . .193
Fig 23. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .198
Fig 24. Receive filter block diagram. . . . . . . . . . . . . . . .200
Fig 25. Receive Active/Inactive state machine . . . . . . .204
Fig 26. Transmit Active/Inactive state machine . . . . . . .205
Fig 27. USB device controller block diagram. . . . . . . . .217
Fig 28. USB MaxPacketSize register array indexing . . .233
Fig 29. Interrupt event handling. . . . . . . . . . . . . . . . . . .244
Fig 30. UDCA Head register and DMA Descriptors. . . .256
Fig 31. Isochronous OUT endpoint operation example .264
Fig 32. Data transfer in ATLE mode. . . . . . . . . . . . . . . .265
Fig 33. USB Host controller block diagram . . . . . . . . . .271
Fig 34. USB OTG controller block diagram . . . . . . . . . .275
Fig 35. USB OTG port configuration . . . . . . . . . . . . . . .276
Fig 36. USB host port configuration. . . . . . . . . . . . . . . .277
Fig 37. USB device port configuration . . . . . . . . . . . . . .277
Fig 38. USB OTG interrupt handling . . . . . . . . . . . . . . .287
Fig 39. USB OTG controller with software stack . . . . . .288
Fig 40. Hardware support for B-device switching from
peripheral state to host state . . . . . . . . . . . . . . .289
Fig 41. State transitions implemented in software during
B-device switching from peripheral to host . . . .290
Fig 42. Hardware support for A-device switching from host
state to peripheral state . . . . . . . . . . . . . . . . . . .292
Fig 43. State transitions implemented in software during
A-device switching from host to peripheral . . . .293
Fig 44. Clocking and power control . . . . . . . . . . . . . . . .296
Fig 45. Auto-baud a) mode 0 and b) mode 1 waveform 312
Fig 46. Algorithm for setting UART dividers. . . . . . . . . .315
Fig 47. UART0, 2 and 3 block diagram . . . . . . . . . . . . .318
Fig 48. Auto-RTS Functional Timing . . . . . . . . . . . . . . .329
Fig 49. Auto-CTS Functional Timing . . . . . . . . . . . . . . .330
Fig 50. Auto-baud a) mode 0 and b) mode 1 waveform 335
Fig 51. Algorithm for setting UART dividers . . . . . . . . . 337
Fig 52. UART1 block diagram. . . . . . . . . . . . . . . . . . . . 343
Fig 53. CAN controller block diagram . . . . . . . . . . . . . . 346
Fig 54. Transmit buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 347
Fig 55. Receive buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 348
Fig 56. Global Self-Test (high-speed CAN Bus
example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Fig 57. Local self test (high-speed CAN Bus example). 349
Fig 58. Entry in FullCAN and individual standard identifier
tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Fig 59. Entry in standard identifier range table . . . . . . . 376
Fig 60. Entry in either extended identifier table. . . . . . . 377
Fig 61. ID Look-up table example explaining the search
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Fig 62. Semaphore procedure for reading an auto-stored
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
Fig 63. FullCAN section example of the ID look-up
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Fig 64. FullCAN message object layout . . . . . . . . . . . . 388
Fig 65. Normal case, no messages lost . . . . . . . . . . . . 390
Fig 66. Message lost. . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Fig 67. Message gets overwritten . . . . . . . . . . . . . . . . . 391
Fig 68. Message overwritten indicated by semaphore bits
and message lost . . . . . . . . . . . . . . . . . . . . . . . 392
Fig 69. Message overwritten indicated by message lost393
Fig 70. Clearing message lost. . . . . . . . . . . . . . . . . . . . 394
Fig 71. Detailed example of acceptance filter tables and ID
index values . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Fig 72. ID Look-up table configuration example (no
FullCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Fig 73. ID Look-up table configuration example (FullCAN
activated and enabled) . . . . . . . . . . . . . . . . . . . 400
Fig 74. SPI data transfer format (CPHA = 0 and
CPHA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Fig 75. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . 412
Fig 76. Texas Instruments Synchronous Serial Frame
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer . . . . . . . . . . . . . . . . . . . . 415
Fig 77. SPI frame format with CPOL=0 and CPHA=0 (a)
Single and b) Continuous Transfer) . . . . . . . . . 416
Fig 78. SPI frame format with CPOL=0 and CPHA=1. . 417
Fig 79. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Single and b) Continuous Transfer) . . . . . . . . . 418
Fig 80. SPI Frame Format with CPOL = 1 and
CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Fig 81. Microwire frame format (single transfer) . . . . . . 420
Fig 82. Microwire frame format (continuos transfers) . . 421
Fig 83. Microwire frame format setup and hold details . 421
Fig 84. I
2
C-bus configuration. . . . . . . . . . . . . . . . . . . . . 431
Fig 85. Format in the Master Transmitter mode . . . . . . 433
Fig 86. Format of Master Receiver mode . . . . . . . . . . . 433
Fig 87. A Master Receiver switches to Master Transmitter
after sending repeated START . . . . . . . . . . . . . 434
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