UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 587 of 841
31.1 Basic configuration
The GPDMA is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCGPDMA.
Remark: On reset, the GPDMA is disabled (PCGPDMA = 0).
2. Clock: see Table 38
.
3. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
4. Programming: see Section 31.6
.
31.2 Introduction
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA
transfers for a single source and destination. For example, a bi-directional port requires
one stream for transmit and one for receives. The source and destination areas can each
be either a memory region or a peripheral.
31.3 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers are
supported.
• GPDMA supports the SSP, I2S, UART, A/D Converter, and D/A Converter peripherals.
DMA can also be triggered by a timer match condition. Memory-to-memory transfers
and transfers to or from GPIO are also supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8-bit, 16-bit, and 32-bit wide transactions.
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
Rev. 3 — 19 December 2013 User manual
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